Hello to everyone,
I have a question for you to ask which has to do with developing and synthesizing hardware using Xilinx EDK, Xilinx ISE and Modelsim. I have spent the last months to edit an existing PCI <-> Wishbone bridge to make it PCI <- IPIF and this process is now complete. I have edited the testbench as well and all testcases pass successfully in post PNR (timing) simulation as generated by Xilinx ISE 6.3.
My next step is to connect a PowerPC powercessor (PPC405 - as generated by Xilinx EDK) to the bridge to test it. For this, i have created a simple project in Xilinx EDK 6.3, generated a PLB2IPIF module, and instructed the project to export the IPIF signals so after exporting to ISE i can easily connect the top module (system.v - not system_stub.v because the PPC is a sub module in my design). This was done with no problems, since i was guided by a colleague who had done this before. It required not-easy-to-think-of stuff.
Anyway, i have exported the PowerPC project to ISE with no problems, connected the bridge to the IPIF signals exported by the PowerPC and to a PCI bus with behaviorial devices. During implementation of the design i get some warnings about signals with no load, in some EDK generated modules, that i am not sure if i can do anything about. For simulation, i use Modelsim SE 6 with the swift dll included in the veriuser variable. In there, the connection seems to be fine, as the PowerPC (actually the PLB2IPIF module) sends the reset and clock fine.
My problem comes to how can i make the PowerPC execute simple software. I tried to edit the C source file of the TestApp automatically generated by EDK when making a new project, to include an int* to which i give addresses and values to these addresses. These addresses are in the bridge's address space, as i have supplied in EDK. I have a single bram memory for instruction and data, which is in the range 0xffffc000 - 0xffffffff. The linker script (which also came with the TestApp) seems to have the range ok. In EDK, i "build all user applications" and include the generated .elf file into the ISE project, as well as system.bmm under system.v
The problem is that the PPC won't execute the software during Modelsim post PNR (as generated by ISE) simulation. At the waveform i see that the EN_A signal is only active for five clock edges (whereas the software i've written is longer than that). At the first and second clock edge, the A address input is zzzzZffc, while at the last three zzzzZff4. Data out (of port A) is always 0.
Before all that, i have asserted the PPC's reset input for a few clock edges and then the PPC starts the above accesses after a few cycles after reset deassertion.
So, what am i missing? What do i have to do to make the PPC execute the software application projects in EDK?
Thank you very much in advance, George Michelogiannakis
