Question

how do i write VHDL code to divide a clock by even integers

Asked by: arunkumarmanas

Hi Experts,
I am trying to write a VHDL code to divide Clock by 2n where n varies from 0 to 255.
I am successful in dividing the clock by 2
Eg: if  i give  the clk as 40Mhz
it should divide by 2n
ie 40 /2 =20 Mhz     this i m getting
40/2*(2) = 10 Mhz     this also i m getting but for later n valve(n=3) i should get
40 /2*(3)= 6.6 Mhz      ( but i m not getting this value with the code i ve written for divide by2 clk)  
40/2*(4)=5 Mhz
40/2*(5)=4Mhz
40/2*(6) =3.3Mhz....... this way i should get the result

i m simply getting 20,10,5,2.5...just its getting divided by 2  ...(this clk divide by 2 code i have with me long back)
but i need clk divide by 2n

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Asked On
2009-02-01 at 04:52:39ID24102634
Tags

vhdl

,

hdl

,

clock

,

divider

Topics

MatLab Programming Language

,

Miscellaneous Programming

,

Microsoft Excel Spreadsheet Software

Participating Experts
2
Points
500
Comments
9

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Answers

 

by: LukeyJayPosted on 2009-02-02 at 18:09:58ID: 23533508

Hi.

I don't know anything about VHDL.  But it seems the problem with your code could be very simple.  What you say you want is to divide by (2*n).  What it looks like you're doing is dividing by (2^n).  Double check your code and make sure it's a multiply symbol (*) between the 2 and the n, and not a power (^) symbol.

Luke

 

by: HappyParrotPosted on 2009-02-20 at 12:12:49ID: 23695712

Just create a simple counter process that will count n ticks of your main clock for each logic level and each time the counter reaches zero, change your output clock state.
This is good for simulation, for synthesis I would reduce the comparator size (the one comparing if the counter has reached zero) by inverting the count direction, increasing the counter size by 1 bit more (this bit will become '1' when your counter  reaches it's maximum desired value) and comparing just that last bit to '1'.

library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
entity divider is
	generic (
	n : integer := 2
	);
	port (
	clk :in STD_logic;
	clk_out :out STD_Logic
	);
end divider;		
 
architecture divider_arc of divider is
signal int_clk: STD_logic := '0';
begin
	clk_out <= int_clk;
clock_divide: process (clk)
	variable counter : integer := n-1;
	begin
		if(rising_edge(clk))then
			if(counter = 0)then
				counter := n-1;
				int_clk <= not int_clk;
			else
				counter := counter - 1;
			end if;
		end if;
	end process clock_divide;
end divider_arc;

                                              
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by: HappyParrotPosted on 2009-02-28 at 12:42:32ID: 23765265

BTW: I don't think this question has anything to do with Microsoft or any zone related to it, being a question about Hardware Description Language.

 

by: LukeyJayPosted on 2009-06-14 at 22:21:49ID: 24626442

The problem the user described did not seem algorithmic in nature.  As I described in my response to the question, it seemed more like a coding error.  Since the user never posted a code example, and never responded to the postings, I suspect my intuition was right, and that the fix was that simple.  So I feel like I probably solved the user's problem, and should perhaps get some credit for the time spent in doing so.  While HappyParrot's answer was thorough, I don't think it was what the user was looking for, nor really addressed the true problem the user was describing, which seemed in truth a very simple one.

 

by: HappyParrotPosted on 2009-06-15 at 08:47:01ID: 24630034

I don't mind the points but for the sake of argument would like to state one thing (i'll try to bee short). If you examine the example arunkumarmanas provided he was actually trying to divide by 2*n and not 2^n.
As he stated:
40 MHz clock divided by 2*n:
40/2*1 = 20 MHz
40/2*2 = 10 MHz
40/2*3 = 6.667 MHz
and so on... thus, and this is my humble opinion he had an algorithmic problem, but not the one you implied.
He wanted to divide hardware clock by an integer number and to receive a syncronized one with lower frequency. Or at least that is how I understood the case. But again that is just me.

20120131-EE-VQP-002

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