Just create a simple counter process that will count n ticks of your main clock for each logic level and each time the counter reaches zero, change your output clock state.
This is good for simulation, for synthesis I would reduce the comparator size (the one comparing if the counter has reached zero) by inverting the count direction, increasing the counter size by 1 bit more (this bit will become '1' when your counter reaches it's maximum desired value) and comparing just that last bit to '1'.
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by: LukeyJayPosted on 2009-02-02 at 18:09:58ID: 23533508
Hi.
I don't know anything about VHDL. But it seems the problem with your code could be very simple. What you say you want is to divide by (2*n). What it looks like you're doing is dividing by (2^n). Double check your code and make sure it's a multiply symbol (*) between the 2 and the n, and not a power (^) symbol.
Luke