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Detecting size of L2 Cache,...

Posted on 1998-09-24
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Last Modified: 2010-04-06
kind of tag-RAM, type and acces rates of RAM.

purpose: determine if the current config makes sense (cacheable area...)

Windows 9x & Windows NT

can anybody help me with this?
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Question by:BlackDeath
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by:BlackDeath
ID: 1340771
Edited text of question
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by:inter
ID: 1340772
I can not find any info but I know that on Pentium II systems the L2 cache is built into the processor assembly, and handles the cache function for up to 2GB of DRAM. So for only pentium II we may make sure that the current config makes sense.
regards, igor
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by:BlackDeath
ID: 1340773
hi, igor.

yo (with pentium II).

you cannot find any info: at home or any url?
i dunno which keyword to use in order to retrieve senseful results.
when i'm looking for "+l2 +cache +detection" i get tons of crap but not what i'm looking for.
i'd be very thankful if you'd keep on looking & post it here when found anything...

thanxsofar & til l8r,

Black Death.
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by:inter
ID: 1340774
Hi again,
I mean there is no relevant info-I think I know what you want-. I found how to detect it on MAC but not on PC.(there is no registry entry on pc either rather than a Session Managers Memory Manager caching)...I am on the subject...
c.u. igor
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jecksom earned 400 total points
ID: 1340775
Hi , BlackDeath !

I didn't found standart function to determinate secondary cache size , it's vary
from one vender to other + you must also select Chipset , example :

Bitfields for Intel 82437/82439HX cache control register:
Bit(s)  Description    
 7-6    secondary cache size
        00 none
        01 256K
        10 512K
        11 reserved,

guess PII with 440LX , BX , NX , etc would be different also.

I can show you how to do this for VIA Technologies and Intel (different functions),
and selected chipset. O'coz , you can also check out "Interrupt list" yourself ,
(INT 1A,AX - B10A : PCI BIOS v2.0c+ - READ CONFIGURATION DWORD)

Best way , as far as i could see, would be checking data transfer time from
one point of memory to other with incremeting write/read block by 64KB.
In the point where transfer slow down more than 20% from previous same operation it
will be end of L2 cache.
if  previous_time/100*20+previous_time)/64KB_block_prev<current_time/64KB_block_cur
then L2_cache continue

Jecksom
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by:BlackDeath
ID: 1340776
hoi, jecksom.

afa interrupts are concerned, i doubt it would work with nt.

regarding your 2nd suggestion (measure transfer times):
i think this can only work if there's more ram installed than cacheable.
if this is so, then how will you detect the slowing down of data transfer when it won't occur?

or didn't i dig your answer?


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by:jecksom
ID: 1340777
Hehe ,

Hm, no, PCI BIOS doesn't depend from NT , WIN9X , UNIX or whatever , o'coz if you
didn't reverse engeenered your Flashed ROM and cleared 1A BIOS interrupt support ;)

2nd : Well ,  as i remember WIN95 required 8 MB memory (!MB) minimal , and currently
x86 L2 caches have maximum 2MB (Klamath - 256 or 512KB) , so i sure it possible
allocate 2MB*2 to test on it ! (o'coz, if you talking about x86, not things like some models of SUN with have up to 2GB! caches already :) )

Jecksom

PS :By the way , looks like Linux using this (transfer time) metod to determinate L2 cache size.

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by:BlackDeath
ID: 1340778
well, i'll give it a try. i'll be back soon. thanxsofar.


Black Death.
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by:BlackDeath
ID: 1340779
hi, jecksom.

sorry i didn't reply for so long.
i couldn't get this (determining cache size by data transfer rate) to work. would you be so nice as to post a code example in form of a function returning a value indicating the size of l2 cache? if you do so and i get it to work i'll increase to 100 and rate a.

tia & sorry again.

Black Death.
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by:jecksom
ID: 1340780
hi BlackDeath!

Here is procedure :

procedure TForm1.Button1Click(Sender: TObject);
var L2_size:byte;L2_size_str:string;
begin
asm
mov eax,2
db  0fh, 0a2h //CPUID
mov L2_size,dl
end;
case L2_size of
$40:L2_size_str:='No L2 Cache';
$41:L2_size_str:=
    'Unified cache, 32 byte cache line, 4-way set associative, 128K';
$42:L2_size_str:=
    'Unified cache, 32 byte cache line, 4-way set associative, 256K';
$43:L2_size_str:=
    'Unified cache, 32 byte cache line, 4-way set associative, 512K';
$44:L2_size_str:=
    'Unified cache, 32 byte cache line, 4-way set associative, 1M';
$45:L2_size_str:=
    'Unified cache, 32 byte cache line, 4-way set associative, 2M';
end;
showmessage(l2_size_str);
end;

  I must give you appologizes , i've tryed my own ( :) memory transfer time) method and
failed , so i guess this solution could be more useful for ya . I also must warn you
to detect L2 cache size using this method (CPUID) on IDT , RISE , CYRIX , AMD CPUs,
they little bit different, if they ever exist .
  In this example i've showing only L2 cache size , i can give you all info that i found over
inet + books+PDFs , so you can detect some required conditions , ie :
CPUID opcodes  supported ? ,
CPU family,
L1 cache size,
preventing crashs on different x86 platforms,
etc;

Jecksom

PS: i also feel that you already known CPUID method :)  

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Author Comment

by:BlackDeath
ID: 1340781
hi, jecksom.

i've tested this on my ppro 200 - it works on 95 and nt.
i've tested it on several other machines -
well, sometimes it works, sometimes not (External Exception) - all intel x86.

>>
  In this example i've showing only L2 cache size , i can give you all info that i found over
       inet + books+PDFs , so you can detect some required conditions , ie :
       CPUID opcodes  supported ? ,
       CPU family,
       L1 cache size,
       preventing crashs on different x86 platforms,
       etc;
<<

would you mail me these info, please?
andreas.naguschewski@vt.siemens.de

tia,

Black Death.
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Author Comment

by:BlackDeath
ID: 1340782
thanxalot.

where did you get this pdf from?
is there more info like that?

thanx for your offer regarding your eMail.
i'll most porbably make use of it...

thanx again & have a nice day,

Black Death.
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