Fetch, Decode, Execute....
I was taught back at school, that there were 3 main CPU cycles: Fetch, Decode and Execute.But now in the course I'm doing they include a fourth, Store.
Is this right?
Has anyone got any usefull information about it?
Are there any intruction's that are exceptions to the 'Store' psrt of the cycle?
Is this right?
Has anyone got any usefull information about it?
Are there any intruction's that are exceptions to the 'Store' psrt of the cycle?
ASKER
I see. Are there any instructions that don't store anything?
Output to a port springs to mind...
Output to a port springs to mind...
ASKER CERTIFIED SOLUTION
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> Are there any intruction's that are exceptions to the 'Store' psrt of the cycle?
Sure. "Test I/O" sets the "condition-code", and "Branch" changes the "next-instruction-address"
This 'BC 0,0' is a two-byte instruction, and often is used when it is necessary that the following instruction must be aligned on a four-byte boundary.
Sure. "Test I/O" sets the "condition-code", and "Branch" changes the "next-instruction-address"
This 'BC 0,0' is a two-byte instruction, and often is used when it is necessary that the following instruction must be aligned on a four-byte boundary.
What you should be able to tell from this discussion is that the answer, like in so many things, it "it depends".
Some bipolar micros of the 80's had a single cycle, and within-chip sequencing was handled purely through propagation delays. I think some embedded RISC chips continue this practice. On Harvard architecture chips, there are different flavors of "store" which are very different from the chip's perspective. Chips like the PIC seem to include both these extremes.
So the answer to your question depends very much on the particular part.
Some bipolar micros of the 80's had a single cycle, and within-chip sequencing was handled purely through propagation delays. I think some embedded RISC chips continue this practice. On Harvard architecture chips, there are different flavors of "store" which are very different from the chip's perspective. Chips like the PIC seem to include both these extremes.
So the answer to your question depends very much on the particular part.
ASKER
They're all good answers, unfortunatly I don't know who to post the points too, a vote anyone?
I decline -- award the points to somebody else ... Otta.
ASKER
Otta, you should back up your request with some concreate evidence, as production of curiosity without satisfactory resolution is highly unfair! (I'm nosey about your reason!Please, please, eloborate :)
But, o.k., I'll award the points tooooooooooo....
3rsrichard, because you've supplied me with the most information, ta!
But, o.k., I'll award the points tooooooooooo....
3rsrichard, because you've supplied me with the most information, ta!
Why thank you. I will cherish them.
> production of curiosity without satisfactory resolution is highly unfair!
Never look a gift-horse in the mouth. :-)
Other than getting a free E-E T-shirt for accumulating 100000 points, I don't know what else I would do with another 50 points. :-)
Never look a gift-horse in the mouth. :-)
Other than getting a free E-E T-shirt for accumulating 100000 points, I don't know what else I would do with another 50 points. :-)
"A machine cycle consists of a sequence of 6 states, numbered S1
through S6. Each state time lasts for two oscillator periods. Thus a
machine cycle takes 12 oscillator periods or 1þs if the oscillator
frequency is 12MHz."
Some instructions can be short, like your first description. Something like incrementing a register.
A much longer type would be moving one memory location to another, where you have to fetch and decode to know what to do, then fetch from external memory then store to external memory.