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Hardware Architecture

Posted on 2000-04-05
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Dear friends, i have the following question about hardware: Suppose a machine had a clock rate of 16 Mhz and memory access time was 100 ns. How many clock pulses would pass waiting to fetch an operand from memory? What would it be for 150 ns memory? 80 ns memory?? Any help to calculate it??? or Explanation please??

Regards,

Jairo Cardenas
Colombia
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by:SysExpert
ID: 2688120
It used to be simple to calculate. Today it is very processor dependent.
With the advent of pre-fetch and a number of other mechanisms designed to speed up memory access, I would need exact CPU, front and side bus speeds and more to get a calculation.
You can find the info on Intel's site in the processor manual.
I hope this helps.
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by:pjknibbs
ID: 2688911
In addition, the 80ns etc. only refers to the time it takes to pull the *first* byte from memory--most modern memory chips allow burst mode operation where they can read a whole batch of, say, 32 bytes at a time with only one clock cycle between each byte. This is how a processor fills its caches when reading memory.
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by:RoadWarrior
ID: 2689190
IF you are thinking of constructing a machine with a 16 Mhz processor, bear in mind that you could get 100-150 ns SRAM fairly cheaply, which would save processor time on the refresh cycles.
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by:RoadWarrior
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Hmmmm I was just thinking about it empirically, and it occurred to me that it probably takes the same amount of time in each case for a lot of 16Mhz procs, I had a 286/16 board, with 150ns DRAM on it, there was no wait state setting in those days, I expanded it with 200ns DRAM and it worked fine apart from on hot days, when it would start to glitch. So for that particular 16Mhz processor on that particular motherboard, the speed of RAM required for 1 memory operation per clock cycle must have been around 180-190ns or so. Of course, for all I know about that particular design, it might have been running the CPU asynchronous, having the chipset and memory at the ISA bus speed of 8mhz. Anyhow, what I am saying really, is that if you just chose those values for illustration, they might not illustrate much.

Road Warrior
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by:jcardenas
ID: 2689552
Sysexpert is clear with the answer, but what kind of data need to calculate, and how can calculate it??? On the Intel Site don´t exist this information. And some Computer Architecture Books don´t have.

Regards,

Jairo Cardenas
Colombia
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by:SysExpert
ID: 2690001
I am sure the data exists, but it may be somewhere you are not looking.
This is now a design problem, so it would probably be under motherbard, chipset design, rather that CPU's.
Look to download an SDK toolkit of some kind that an OEM would use to create a motherboard using INTEL chips.

With todays integrated chipsets, you no longer worry about the CPU fetch speed, but the chipset that handles memory cache,SDRAM and any other memory management. Motherboard manufacturers need this to recommend the type of RAm for the MB implementation.
You have to supply more info if you want more help. This is a design problem today. It was much easier 10 years ago when CPU's were much simpler.
I hope this helps.
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by:jcardenas
ID: 2690468
Sorry, i don´t have more info. On my Computer Architecture book exist it as question and don`t exist more examples.

Regards,


Jairo
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by:SysExpert
ID: 2690666
So this is a question from a course on Computer Architecture.
Well then, since things have changed a lot since the book was written, you are going to have to follow the information provided by the book. It sounds totally outdated to me.
I would download all the manuals for an Intel 386 CPU. The answer should be in there.
I hope this answers your question.
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by:jcardenas
ID: 2691422
Ok, i will try to download the Intel Manuals.

Thanks,

Jairo
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RoadWarrior earned 100 total points
ID: 2695472
Well here goes, but my low level architecture course was based on the Z80 and the 68000 ....
For a simple processor If an operand is one byte large.

The access time given in nanoseconds for RAM is the minimum reliable time to fetch one byte. A nanosecond is 1x10^-9 seconds. One cycle of a processor running at 16Mhz is 1/(16x10^6) = 62.5x10^-9s or 62.5ns therefore acessing 80ns RAM would take 2 whole clock cycles, as would 100ns RAM, 150ns RAM would take 3 whole clock cycles. I think the lesson here is that specifying 80ns RAM would be over engineering it, and cheaper 100ns RAM could be specified comfortably.

Recent processors can do handy tricks like stretching a clock cycle by up to half to wait for things like RAM access, so any processor capable of that would be able to access the first byte in 1 stretched clock cycle, but when fetching a number of single bytes would then be back to an effective 2 clock cycles.

Road Warrior

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by:RoadWarrior
ID: 2695506
Must still hold good today for single byte access, no matter what block and burst transfer modes exist , for synchronous performance on a 100MHZ bus, that calculation gives minimum 10ns SDRAM required, which is right, though for reliability 8ns is desirable. And for 133Mhz, 7.5ns minimum, which means 7ns parts just work and 6ns is better for comfort.

For anyone out there figuring out cache speed requirements for 486 boards, though, there is usually a 74F244 buffer between the cache and the CPU, which loses 8-10ns propagation delay, so you have to get faster chips than might seem necessary. Really old boards sometimes have a LS244 which loses you 15ns.

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by:jcardenas
ID: 2696092
Thanks for your excellent answer, by me is clear this concept. My text book is not clear with it, only show bad explanation without calculation.

Thanks,

Jairo Cardenas
Colombia
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