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VC++ nmake questions

Posted on 2001-06-13
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Last Modified: 2012-06-21
what is the meaning of
the following which is from makefile for VC++

.cpp{$(INTDIR)}.obj::
   $(CPP) @<<
   $(CPP_PROJ) $<
<<


is this compatible with GNU make?

thx
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Question by:Phoebe
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6 Comments
 
LVL 86

Expert Comment

by:jkr
ID: 6187054
The above is an inference rule - it has the form of

.fromext.toext:
commands

doc quote:
"The fromext represents the extension of a dependent file, and toext represents the extension of a target file. Extensions are not case sensitive. Macros can be invoked to represent fromext and toext; the macros are expanded during preprocessing. The period (.) preceding fromext must appear at the beginning of the line. The colon (:) is preceded by zero or more spaces or tabs. It can be followed only by spaces or tabs, a semicolon (;) to specify a command, a number sign (#) to specify a comment, or a newline character. No other spaces are allowed. Commands are specified as in description blocks."


'$(SYMBOL)' is a macro expansion

'<<' specifies an inline file, and '$<' refers to a dependant file in the project.

So, the rule mainly reads "create .obj files from .cpp files by using the command given in '$(CPP)' taking care of the dependant file specified in '$(CPP_PROJ)'"

And: No, this is not compatible with the BSD 'make'
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LVL 86

Expert Comment

by:jkr
ID: 6187064
>> is this compatible with GNU make?

Sorry for the confusion, but GNU 'make' is actually BSD 'make', so the answer is still 'no'.
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Accepted Solution

by:
abesoft earned 300 total points
ID: 6187622
Two part answer.... In this rule, there is a header (the first line) and a command.  

First, the header:

This rule is a "generic rule", to transform a .cpp file into a .obj.  To do the same thing in GNU make, you would use:

%.obj : %.cpp
        $(CC) -c $(CFLAGS) $(CPPFLAGS) $< -o $@

The syntax is definitely different between the two, but they can (for the most part) do the same things.

Secondly, the command:
The rest of the rule says what to do to turn a .cpp file into a .obj.  It reads as follows:
  $(CPP) @<<
  $(CPP_PROJ) $<
<<

The @<< {filler} << syntax tells make to create a tempfile, write all of the {filler} into it, and then stick its name on the command-line after the @.  This will likely turn into:
  cl.exe @tempfile.000
MS uses the @foo syntax to make the compiler read in arguments from the named file.  Other compilers use other syntax, so check with your compiler.

Under UNIX, you don't need to worry about command-line length, so redirecting the command-line via a temp file isn't important.  If you want to do it, you can though.  Try something like:

%.obj : %.cpp
        echo $(CPP_PROJ) $< > args.txt
        type args.txt | $(CPP)
        del args.txt

(I'm using type instead of cat, and del instead of rm.  I assume that you are running the make under DOS, not UNIX.  You will need to tweak this for your actual OS.)

Hope this helps!
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Author Comment

by:Phoebe
ID: 6190902

abesoft's answer is better.

although jkr's answer is helpful.

thank you guys for open my sense.
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Author Comment

by:Phoebe
ID: 6219784
It should change to PAQ
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Author Comment

by:Phoebe
ID: 6219790
It should be PAQ
0

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