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makefile and conditional compilation

Posted on 2002-05-23
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Last Modified: 2008-03-06
I have an application with *many* source files that can be compiled "normally" or with a "debug" option.
The compilation is dependant on the -DDEBUG compiler switch.

How can I set up a makefile so that I can type in either:

make app_debug (to make the debug version)
or
make app (to make the non-debug version)

Basically the problem is this:
Once I make the debug version (using the -DDEBUG switch) the object files are timestamped as being younger than the source files. So when I try to make the non-debug version nothing gets "re-compiled".

Currently I link the source files to different names which causes differnet object file names to be created.

i.e.
I link source.c to source_d.c
so that
source.c compiles to source.o
source_d.c compiles to source_d.o

I think this is a clumsy way to do waht I need, can anyone suggest a more elegant approach?

Paul
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Question by:zebada
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Expert Comment

by:jkr
ID: 7030905
You could just specify a different output path for each target like e.g. VC++ does - this would keep the (equally named) object files n different directories, so that no time-stamp confusion would take place...
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Expert Comment

by:Axter
ID: 7030925
You can also change the name of the output targets.
For example, all the debug versions you can name foo.debug_o and release version foo.o
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Author Comment

by:zebada
ID: 7030991
The real question is how do I do that in the makefile?

I am currently using my own implicit .c.o: rule to compile my c source files.
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Expert Comment

by:Axter
ID: 7031024
Is this for Unix/Linux or Dos?
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Expert Comment

by:Axter
ID: 7031027
If you're doing Unix/Linux, you can create two script files.

One haveing the following:

#*********************************************************
# Set environmental variable
setenv REL_OR_DBUG debug_
# Launch make file with commandlines given to script file
make NameOfMyMakeFile %1 %2 %3 %4 %5
#*********************************************************

The other script file can be the following:
#*********************************************************
# Set environmental variable
setenv REL_OR_DBUG ""
# Launch make file with commandlines given to script file
make NameOfMyMakeFile %1 %2 %3 %4 %5
#*********************************************************


Then in your make file have the following:
PRGSUB = $(CSRCS:cpp=$(REL_OR_DBUG)o)
PRG  = $(PRGSUB:c=$(REL_OR_DBUG)o)
OBJS = $(PRG)
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Expert Comment

by:Axter
ID: 7031035
You can also just do one script file and make the first command line argument the environmental variable for REL_OR_DBUG.

Example:
#*********************************************************
# Set environmental variable
setenv REL_OR_DBUG %1
# Launch make file with commandlines given to script file
make %2 %3 %4 %5 %6 %7
#*********************************************************

You would call the above script file in the following manner.

MyScriptFileName debug_ NameOfMyMakeFile

If you have additonal command lines just added to the end.
Example:

MyScriptFileName release_ NameOfMyMakeFile buildme

Or

MyScriptFileName rel_ NameOfMyMakeFile clean

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Expert Comment

by:Axter
ID: 7031045
Correction on the makefile syntax:

PRGSUB = $(CSRCS:cpp=${REL_OR_DBUG}o)
PRG  = $(PRGSUB:c=${REL_OR_DBUG}o)
OBJS = $(PRG)

It may be hard to tell with the fonts on this web site, but the REL_OR_DBUG variable has "curly cue" {} wrapped around them.
Environmental variables get curly cues {}, and NOT the parenthesis "()" that normal make file variables get.
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Author Comment

by:zebada
ID: 7031248
Platforms:
SCO
HP-UX
Solaris
Tru64 (DEC Alpha OSF1)
Linux
AIX

If I have something like this in my makefile:

HDR=            a.h b.h c.h

SRC=            a.c b.c c.c

OBJ=            $(SRC:.c=.o)

prog:           $(OBJ)

$(OBJ):         $(HDR)

This is my .o.c: rule:
.c.o:           $<
                $(CC) $(ALL_CFLAGS) -c $<

How can I make the $(CC) command output to the different object file names (for debug and non-debug) based on the value of an env variable?

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Accepted Solution

by:
Axter earned 50 total points
ID: 7031781
Here's a section of one of my old make files.
Just ignore what you don't need.
If you're interested, I can also show you how to make different targets, depending on your unix platform, by using `uname`


######################################################################
.SUFFIXES: .c .cpp .h .$(REL_OR_DBUG)o

.cpp.$(REL_OR_DBUG)o:; @echo "$(<:cpp=cpp):1: Creating: Object File from *.cpp" ${XPLATFORMX}/${COMPILER_OBJECT_ID}/$(<:cpp=$(REL_OR_DBUG)o)"..."
     $(CXX) $(CXXFLAGS) -c $< -o ${XPLATFORMX}/${COMPILER_OBJECT_ID}/$(<:cpp=$(REL_OR_DBUG)o)
     cp -fp -- ${XPLATFORMX}/${COMPILER_OBJECT_ID}/$(<:cpp=$(REL_OR_DBUG)o) ${XPLATFORMX}/${COMPILER_OBJECT_ID}/../..

.c.$(REL_OR_DBUG)o:; @echo "$(<:c=c):1: Creating: Object File from *.c" ${XPLATFORMX}/${COMPILER_OBJECT_ID}/$(<:c=$(REL_OR_DBUG)o)"..."
     $(CC) $(CFLAGS) -c $< -o ${XPLATFORMX}/${COMPILER_OBJECT_ID}/$(<:c=$(REL_OR_DBUG)o)    
     cp -fp -- ${XPLATFORMX}/${COMPILER_OBJECT_ID}/$(<:c=$(REL_OR_DBUG)o) ${XPLATFORMX}/${COMPILER_OBJECT_ID}/../..

)
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Expert Comment

by:Axter
ID: 7043261
zebada,
Did the above script code answer your question?
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Author Comment

by:zebada
ID: 7043269
I'll take a look at it later this week - been too busy.
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Expert Comment

by:Axter
ID: 7043274
OK
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Author Comment

by:zebada
ID: 7171575
Thanks Axter,
Sorry it took so long - the project finally got the go-ahead to redesign the make files.
The suffix substitution did the trick :)
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Expert Comment

by:Axter
ID: 7171924
Glad to be of help.
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