[Webinar] Streamline your web hosting managementRegister Today

  • Status: Solved
  • Priority: Medium
  • Security: Public
  • Views: 388
  • Last Modified:

Filling the memory banks

I remember back when I was studying hardware about when using SIMMs and older DIMMs you would need to use more than one in order to fill the memory bank. (i.e. Need four 8-bit SIMMs to fill the bank of a 32-bit 486 CPU).

What I've been trying to figure out is, is this still an issue? RIMM's are 16-bit but you don't need eight of them to fill a bank for a 128-bit P4. (By the way, is a P4 really 128 bits? I read it somewhere but haven't been able to confirm it anywhere else).
1 Solution
You have to use 2 rimms because that is how the p4 acives the high bus speed.  Take a look at toms hardware, it has tons of info on this stuff.
Kyle SchroederEndpoint EngineerCommented:
RIMMs must be installed in pairs as rrhunt indicated due to the nature of the RAMBUS architecture used.  If you have 4 slots and they are not all populated by RIMM modules, you need to install dummy terminator chips in the other 2 slots.  Sometimes these are included with the RIMM purchase, but generally must be purchased seperately (unless you already have them).

DDR and normal SDRAM (PC133, etc) do not require this method.

On the DDR front some newer chipsets that support DDR ram will support a feature that accesses the ram in a "dual channel" mode that interleaves the data between the two sticks.  Now, while on these chipsets it doesn't require the use of two sticks, but the use of a matched pair of DDR DIMMS can give a performance increase (especially with a P4 on the Granite Bay chipset.)  With the Dual Channel DDR it really has nothing to do with bit width, but it just alternates pages between the two sticks (or, it might split the page, but I haven't found much in depth technical info on how it interleaves the data, but for the end user it really doesn't matter anyway.)

Some older SDR SDRAM chipsets would also support interleaving, but the front side bus of the processor was often the same speed as the ram, so there was generally little noticable benefit from the interleaving.  That has changed now that Bus speeds can be higher than the output speed of the system ram, especially on a P4 system where the FSB is much faster than standard ram speeds (this can sometimes be achieved on an Athlon system with an overclocked bus, but it's common to reduce system stability with overclocking.)
Will You Be GDPR Compliant by 5/28/2018?

GDPR? That's a regulation for the European Union. But, if you collect data from customers or employees within the EU, then you need to know about GDPR and make sure your organization is compliant by May 2018. Check out our preparation checklist to make sure you're on track today!

RIMMs only need to be installed in pairs on dual-channel RDRAM boards, surely? Older single-channel designs should be able to have them individually with no issue.

In any case Rambus memory is designed as a sort of serial/parallel hybrid, so the idea is that you read 4 16-byte chunks in rapid succession to get the full 64-bit memory read.
Rambus is designed to be put in pairs, if you want to put in only one stick you have to get a dummy stick to pair it with.
For empty Rambus slots you use CRIMMs (Continuity Modules)

They recommend only installing like size memory modules, and modules of the same speed rating.

If you want to look at details of the Pentium 4 check the specs here:
"The Pentium 4 processor expands the floating-point registers to a full 128-bit..."
W"ith the introduction of SSE2, the Intel NetBurst microarchitecture now extends the SIMD capabilities that MMX technology and SSE technology delivered by adding 144 instructions. These instructions include 128-bit SIMD integer arithmetic and 128-bit SIMD double-precision floating-point operations. ..."
leopard_1968Author Commented:
pjknibbs, I think you meant 16-bit rather than 16-byte, but that's what I was looking for, although the discussion about adding RIMMs in twos is very helpful as well.

Thank you TEG for the link to the P4 specs. It did answer my secondary question, although indirectly:

"The Pentium 4 processor's 533-MHz system bus supports Intel's highest performance desktop processor by delivering 4.2 GB of data-per-second into and out of the processor."

If you do the math ((4200MB*8bits/byte)/533MHz), it turns out that a P4 has a 64-bit external data bus afterall.

Featured Post

SMB Security Just Got a Layer Stronger

WatchGuard acquires Percipient Networks to extend protection to the DNS layer, further increasing the value of Total Security Suite.  Learn more about what this means for you and how you can improve your security with WatchGuard today!

Tackle projects and never again get stuck behind a technical roadblock.
Join Now