abelcunha
asked on
Programming QUART SC28C94
I´d lik to know if someone can get me a C example code for programming the SC28C94 QUART.
I'm having some trouble in controlling the internal interrupt system for this UART, specially when I'm detecting the Tx and Rx interrupt.
My problem is that I can attend both interrupts, but after this the interrupt line wont disable and stays active even after I attend the Rx and the Tx interrupt, even though I can see (read the CIR register) that there are no interrupts to be attended to.
If someone can help me in this matter I'd be much obliged
Thank you.
My best regards.
Abel Cunha.
I'm having some trouble in controlling the internal interrupt system for this UART, specially when I'm detecting the Tx and Rx interrupt.
My problem is that I can attend both interrupts, but after this the interrupt line wont disable and stays active even after I attend the Rx and the Tx interrupt, even though I can see (read the CIR register) that there are no interrupts to be attended to.
If someone can help me in this matter I'd be much obliged
Thank you.
My best regards.
Abel Cunha.
ASKER
The interrupt line of the QUART is directly connected to the IRQ5 input line of a PC104 board, via some hardware that I've developed to control RS232 equipment.
The QUART Datasheet indicates that we can substitute the assert of the IACKN line by the command UPDATECIR (outport(0x2A,0xValue)), and I'm doing this whenever I want to see wich of the ocurrences is responsable for the activation of the interrupt line.
I only run out of the Interrupt Service Routine after I can assure that no other interrupt needs to be attended (inport(ISR_address)=0x00)
Despite all this the IRQn line of the QUART remains at low state, wich means that it's still active and waiting to be attended.
The QUART Datasheet indicates that we can substitute the assert of the IACKN line by the command UPDATECIR (outport(0x2A,0xValue)), and I'm doing this whenever I want to see wich of the ocurrences is responsable for the activation of the interrupt line.
I only run out of the Interrupt Service Routine after I can assure that no other interrupt needs to be attended (inport(ISR_address)=0x00)
Despite all this the IRQn line of the QUART remains at low state, wich means that it's still active and waiting to be attended.
ASKER
The interrupt line of the QUART is directly connected to the IRQ5 input line of a PC104 board, via some hardware that I've developed to control RS232 equipment.
The QUART Datasheet indicates that we can substitute the assert of the IACKN line by the command UPDATECIR (outport(0x2A,0xValue)), and I'm doing this whenever I want to see wich of the ocurrences is responsable for the activation of the interrupt line.
I only run out of the Interrupt Service Routine after I can assure that no other interrupt needs to be attended (inport(ISR_address)=0x00)
Despite all this the IRQn line of the QUART remains at low state, wich means that it's still active and waiting to be attended.
The QUART Datasheet indicates that we can substitute the assert of the IACKN line by the command UPDATECIR (outport(0x2A,0xValue)), and I'm doing this whenever I want to see wich of the ocurrences is responsable for the activation of the interrupt line.
I only run out of the Interrupt Service Routine after I can assure that no other interrupt needs to be attended (inport(ISR_address)=0x00)
Despite all this the IRQn line of the QUART remains at low state, wich means that it's still active and waiting to be attended.
ASKER CERTIFIED SOLUTION
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No comment has been added lately, so it's time to clean up this TA.
I will leave the following recommendation for this question in the Cleanup topic area:
Accept: grg99 {http:#9725131}
Please leave any comments here within the next seven days.
PLEASE DO NOT ACCEPT THIS COMMENT AS AN ANSWER!
Tinchos
EE Cleanup Volunteer
I will leave the following recommendation for this question in the Cleanup topic area:
Accept: grg99 {http:#9725131}
Please leave any comments here within the next seven days.
PLEASE DO NOT ACCEPT THIS COMMENT AS AN ANSWER!
Tinchos
EE Cleanup Volunteer
Quite often you have to send an interrupt acknowledge to the interrupt controller chip,
which then sends an interrupt clear signal to the UART. Or in other architectures you directly clear to the UART.