Johncy
asked on
BIOS and option rom?
Hi,
I am using sc1200 that can address upto 4GB physical address). My flash memory is 32Mbit. Generally the ROM chip is mapped in hardware to the high physical address (0xFFFFFFFF - 0xFFC00000). My SDRAM is 32MByte. It is mapped in hardware to CPU address (0x00000000 - 1FFFFFF). My Bios program is kept in the flash memory. After the hardware initialization is done and before going with the int 19h interrupt, my bios program scans for option Rom from location 0xC8000h. So when it starts scanning from location 0xC8000, is any hardware remapping that has to be done.
I am using sc1200 that can address upto 4GB physical address). My flash memory is 32Mbit. Generally the ROM chip is mapped in hardware to the high physical address (0xFFFFFFFF - 0xFFC00000). My SDRAM is 32MByte. It is mapped in hardware to CPU address (0x00000000 - 1FFFFFF). My Bios program is kept in the flash memory. After the hardware initialization is done and before going with the int 19h interrupt, my bios program scans for option Rom from location 0xC8000h. So when it starts scanning from location 0xC8000, is any hardware remapping that has to be done.
Can you please formulate your question ?
ASKER
My bootloader for Flash (ROLO) is kept as option ROM. I am confused with whether the location 0xC8000 is Flash memory location or is the SDRAM location? When it scans for option ROM, does the Flash memory has to be remapped to a different physical address in hardware?
Thanks in advance.
Thanks in advance.
ASKER CERTIFIED SOLUTION
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ASKER
Thanks.
Is my hardware mapping looks right? Should I need a remapping in hardware when it searches for option rom?
Is my hardware mapping looks right? Should I need a remapping in hardware when it searches for option rom?
It may be not "remapping". It is much simpler to connect to DiskOnChip 2 Chip Selects. One for boot:
range 0xFFF80000-0xFFFFFFFF and one for 0x000C8000-0x000DFFFF.
range 0xFFF80000-0xFFFFFFFF and one for 0x000C8000-0x000DFFFF.
ASKER
I use Flash memory to store my bios program, linux OS, filesystem. My bootloader for flash (ROLO) is kept as option ROM.
Something wrong here... Do you have NOR flash for boot or you have only DiskOnChip
for boot your BIOS ?
for boot your BIOS ?
ASKER
I have NOR flash.
So you DO NOT need to map DiskOnChip to 0xFFFFFFFF. Moreover you can not map both
NOR flash and DiskOnChip to same address.
NOR flash and DiskOnChip to same address.
Can you please describe your system again and now with NOR flash ?
ASKER
I have NOR Flash. But if I meet some problem with NOR flash I would like to have diskonchip millennium. I would like to make my software and hardware ready for both purposes. I would use any one and not both at the same time.
ASKER
If I have to use Flash or DOCM, how the mapping of each one should be at power-on?
Same as my response for your other (related) question "real and protected mode":
The BIOS co-exists in the "same" address space as the SDRAM, much the same way as the BIOS in a PC. The ROM or the SDRAM will be enabled as appropriate.
I am not 100% clear on the option ROM, but that "should" hold true also, i.e. the device should know to enable the rom chip select in that case.
I think the key that will unlock this all for you is to look at the schematics in the National reference design, and see how those match your situation.
My response to your other question was:
--------------------------
From the National data sheet I found where the core logic module decodes the FFFFFFF0 address (and some others) and passes it to the sub-ISA interface, where the boot ROM needs to physically connect...
Excerpt:
--------------------------
5.2.5.6 ROM Interface
The Core Logic module positively decodes memory
addresses 000F0000h-000FFFFFh (64 KB) and
FFFC0000h-FFFFFFFFh (256 KB) at reset. These memory
cycles cause the Core Logic module to claim the cycle, and
generate an ISA bus memory cycle with ROMCS#
asserted. The Core Logic module can also be configured to
respond to memory addresses FF000000h-FFFFFFFFh
(16 MB) and 000E0000h-000FFFFFh (128 KB).
8- or 16-bit wide ROM is supported. BOOT16 strap determines
the width after reset. MCR[14,3] (Offset 34h) in the
General Configuration Block (see Table 3-2 on page 86 for
bit details) allows program control of the width.
Flash ROM is supported in the Core Logic module by
enabling the ROMCS# signal on write accesses to the
ROM region. Normally only read cycles are passed to the
ISA bus, and the ROMCS# signal is suppressed for write
cycles. When the ROM Write Enable bit (F0 Index 52h[1])
is set, a write access to the ROM address region causes a
write cycle to occur with MEMW#, WR# and ROMCS#
asserted.
--------------------------
I went here:
http://wwwd.national.com/National/developer.nsf/devices/sc1200.htm
and downloaded the data sheet:
http://wwwd.national.com/National/developer.nsf/files/sc1200/$File/sc1200_ds.pdf
and their reference design:
http://wwwd.national.com/National/developer.nsf/files/sc1200/$File/sc1200_ebga_tft_on_parallel.pdf
The boot rom schematic is located on PDF page 9
Also they have an Orcad DSN, if you can make use of it that should shave some time off your project.
Good Luck,
Paul
The BIOS co-exists in the "same" address space as the SDRAM, much the same way as the BIOS in a PC. The ROM or the SDRAM will be enabled as appropriate.
I am not 100% clear on the option ROM, but that "should" hold true also, i.e. the device should know to enable the rom chip select in that case.
I think the key that will unlock this all for you is to look at the schematics in the National reference design, and see how those match your situation.
My response to your other question was:
--------------------------
From the National data sheet I found where the core logic module decodes the FFFFFFF0 address (and some others) and passes it to the sub-ISA interface, where the boot ROM needs to physically connect...
Excerpt:
--------------------------
5.2.5.6 ROM Interface
The Core Logic module positively decodes memory
addresses 000F0000h-000FFFFFh (64 KB) and
FFFC0000h-FFFFFFFFh (256 KB) at reset. These memory
cycles cause the Core Logic module to claim the cycle, and
generate an ISA bus memory cycle with ROMCS#
asserted. The Core Logic module can also be configured to
respond to memory addresses FF000000h-FFFFFFFFh
(16 MB) and 000E0000h-000FFFFFh (128 KB).
8- or 16-bit wide ROM is supported. BOOT16 strap determines
the width after reset. MCR[14,3] (Offset 34h) in the
General Configuration Block (see Table 3-2 on page 86 for
bit details) allows program control of the width.
Flash ROM is supported in the Core Logic module by
enabling the ROMCS# signal on write accesses to the
ROM region. Normally only read cycles are passed to the
ISA bus, and the ROMCS# signal is suppressed for write
cycles. When the ROM Write Enable bit (F0 Index 52h[1])
is set, a write access to the ROM address region causes a
write cycle to occur with MEMW#, WR# and ROMCS#
asserted.
--------------------------
I went here:
http://wwwd.national.com/National/developer.nsf/devices/sc1200.htm
and downloaded the data sheet:
http://wwwd.national.com/National/developer.nsf/files/sc1200/$File/sc1200_ds.pdf
and their reference design:
http://wwwd.national.com/National/developer.nsf/files/sc1200/$File/sc1200_ebga_tft_on_parallel.pdf
The boot rom schematic is located on PDF page 9
Also they have an Orcad DSN, if you can make use of it that should shave some time off your project.
Good Luck,
Paul
ASKER
This means I can have my Flash memory mapped only to the lower address. Is it correct?
>This means I can have my Flash memory mapped only to the lower address. Is it correct?
Yes, that is correct, addresses connected to AD22..AD0 (assuming you have 4MBx8), /CE connected to /ROMCS, Data connected to AD31..AD24
Yes, that is correct, addresses connected to AD22..AD0 (assuming you have 4MBx8), /CE connected to /ROMCS, Data connected to AD31..AD24