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Pentium III or higher: 64-bit / 128-bit integer operations

Posted on 2003-12-11
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Last Modified: 2008-02-26
Hello,

I would like to implement various mathematical operations using relatively large integers for several highly optimized mathematical analyses in C++.

Are there simple assembly sequences, for Pentium III or higher, to program the following:

1) unsigned 64-bit * unsigned 64-bit multiply with unsigned 128-bit unsigned result.
2) unsigned 128-bit / unsigned 64-bit division with unsigned 64-bit result.
3) 64-bit unsigned + 64-bit unsigned addition with indication of carry.
4) 64-bit unsigned - 64-bit unsigned subtraction with indication of borrow.

I would really like to use SSE2 or something like that, as opposed to complicated sequences with eax:edx, etc. Most of my assembly experience is with 386 and some ID and timing stuff with CPUID and RDTSC stuff. Thus I could really use some help with the newer SSE stuff.

Are there any true 128-bit registers (or some combination registers such as the old eax:edx for old 386) for the new Pentium III and higher processors?

Thank you  very much for any assistance.

Sincerely, Chris.
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Question by:dude_1967
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Expert Comment

by:terageek
ID: 9925362
The PIII only supports SSE, not SSE2.
If you want to work with integers, then you want MMX (SSE works on floats, and each 128 bit register is treated as 4 parallel 32 bit floats).

You can use MMX instructions to manipulate some 64 bit values for addition and subtraction.  I believe that you can multiply 2 64-bit numbers, but you will need to specifiy if you want the low 64-bits of the result or the high 64-bits of the result.  I don't believe you can divide 128 bits by 64 bits however.

http://www.tommesani.com/MMXPrimer.html

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by:dude_1967
ID: 9942661
Dear terageek,

I have been working a while with your suggestions. I think that my question was not clear. In addition, I would like to start with something a bit easier for me. Let's just examine the simple unsigned multiplication of unsigned 32-bit a * unsigned 32-bit b = unsigned 64-bit c.

I have coded this in a mixed C++ / ASM project using VC6, SP5 in the dialect of 386 assembler below.

Can this be done faster using something from the Pentium IV or higher? I was mistaken since I thought the newer stuff with SSE2 was in PIII as well. Let's look at the PIV architecture.

Let's start with this simple example. After mastering the 32 * 32 = 64 stuff, I would like to study the next level (64 bit * 64 bit = 128 bit).

Can you or anyone else please look at the sample and try to get this more modern that the 386 stuff?

Thanks once again for any help.

Sincerely, Chris.

int main(int argc, char* argv[])
{
  unsigned __int32 a = 0x33333333;
  unsigned __int32 b = 0x66666666;

  unsigned __int32 aa = 0xBBBBBBBB;
  unsigned __int32 bb = 0xEEEEEEEE;

  unsigned __int64 c, cc;

  // Multiply c  =  a *  b
  // Multiply cc = aa * bb
  __asm
  {
    mov eax, dword ptr [a]
    imul dword ptr [b]
    mov dword ptr [c], eax
    mov dword ptr [c + 4], edx

    mov eax, dword ptr [aa]
    mul dword ptr [bb]
    mov dword ptr [cc], eax
    mov dword ptr [cc + 4], edx
  }

  // Test c  =  a *  b
  unsigned __int64 t  = static_cast<unsigned __int64>( a) *  b;

  // Test cc = aa * bb
  unsigned __int64 tt = static_cast<unsigned __int64>(aa) * bb;

  // Final check.
  const bool ok = t == c && tt == cc;

  return ok ? 0 : 1;
}
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Assisted Solution

by:terageek
terageek earned 200 total points
ID: 9958278
I am not sure I can give you all of the detailed info you would need here.  Here are a couple of links to get you started...

Intel's page for the P4 has a lot of usefull articles...

http://www.intel.com/cd/ids/developer/asmo-na/eng/microprocessors/ia32/pentium4/optimization/index.htm

You will probably want to start with the P4 instruction set reference to read up on the MMX, SSE and SSE2 instructions...

http://developer.intel.com/design/pentium4/manuals/245471.htm

And if you want to get ahead of the curve, you can start reading up on the 13 new instructions in Prescott (the Pentium V?)

http://www.intel.com/cd/ids/developer/asmo-na/eng/microprocessors/ia32/pentium4/optimization/43988.htm
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Accepted Solution

by:
mtmike earned 300 total points
ID: 9959981
I think the MMX/SSE/SSE2 extensions will not be very useful for what you want to accomplish. Since you are new to them, a short overview...

MMX:

This adds eight 64-bit registers (labelled mm0-mm7) and 54 instructions. The mmx instructions operate on packed dwords, words or bytes. Depending on the instruction, a 64-bit mmx operand is either treated as two dwords, four words or eight bytes. For example:

paddb mm0,mm1 ; add eight packed bytes
paddw mm0,mm1 ; add four packed words
paddd mm0,mm1 ; add two packed dwords

The instruction set contains logical, (saturating) arithmetic, multiplication, data movement, packing/unpacking and comparison operations.

Multiplication is limited to signed words. You can only compute one half of the result at a time:

pmullw mm0,mm1 ; multiply four signed words and store the low word of the result
pmulhw mm0,mm1 ; multiply four signed words and store the high word of the result

Or you can do a widening multiply-add:

pmaddwd mm0,mm1; multiply four signed words and add each pair of results.

The mmx instruction set was later extended with an unsigned multiply (P3):

pmulhuw mm0,mm1 ; multiply four unsigned words and store the high word of the result

So, doing 32 x 32 -> 64 multiply word-wise is certainly going to take a lot more instructions than the plain x86 version. Since mmx has no indication of carry, adding partial results is going to be tricky.

SSE (P3):

This adds eight 128-bit registers (xmm0-xmm7). All new sse instructions operate on packed floats. There is no support for integer arithmetic (only logical and packing instructions).

SSE2 (P4):

This adds support for doubles and some integer instructions. Of interest are:

pmuludq mm0,mm1 ; multiply two unsigned dwords to a qword
pmuludq xmm0,xmm1 ; multiply four unsigned dwords to two qwords

paddq mm0,mm1 ; qword add
paddq xmm0,xmm1 ; add two packed qwords

psubq mm0,mm1 ; qword sub
psubq xmm0,xmm1 ; substract two packed qwords

These might accelerate 32 x 32 -> 64 multiplies since you can do two of them at a time.

A 64 x 64 -> 128 multiply could be implemented by doing four 32 x 32 -> 64 multiplies (two instructions). The partial results will have to be added using plain old "adc" since sse has no carry support. The multiplies will be a little bit more efficient, but you will end up having to do a lot of register transfers.

The paddq/psubq instructions are also unsuitable for your purposes since they give no indication of carry/borrow.

There are no mmx/sse integer division instructions.
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by:dude_1967
ID: 9962644
mtmike, terageek,

Thanks for the clearly thought out and relevant suggestions as well as the advise on further reading. It seems like it could take some careful design and a bit of time to work out the optimal solution. I have split the question points and now consider this topic closed for the purpooses of the forum. I'll continue working on a decent solution.

Thanks again.

Also my complements to the forum---always a source of competent information.

Sincerely, Chris.
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