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Makefile with condition

Posted on 2004-09-30
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Last Modified: 2013-12-26
have a small problem in this makefile
     CC=gcc
                1.o: 1.cpp
     #ifeq ($(kw),y
     $(CC) -o  2.o 2.cpp
     #ifeq ($(kw),n)
     $(CC) -o  1.o 1.cpp
     #endif
     
when I invoke the make file like
make kw=y or
make kw=n or
make
all of these lines will compile the both file
so what I suppose to change to make it for example
make kw=y to compiler file 2.cpp
make kw=n  to compiler file 1.cpp
make by default n
TK

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Question by:albusaidi
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11 Comments
 
LVL 1

Expert Comment

by:gseidman
ID: 12201271
You don't seem to really understand what's going on in a Makefile to begin
with, actually. First off, you are compiling executables but are giving the
resulting files a .o extension, which implies that they are object files.
Second, it looks like you have two separate executable targets and you want
to be able to compile one at a time. Third, these appear to be C++ source
files, but you are trying to compile them with a C compiler. If this is a
correct understanding of the problem, you want

CXX=g++
exe1: 1.cpp
      $(CXX) -o exe1 1.cpp

exe2: 2.cpp
      $(CXX) -o exe2 2.cpp

You can then run

make exe1

to build the first program and

make exe2

to build the second program.

0
 

Author Comment

by:albusaidi
ID: 12201386

actually this is not my problem , I make this small example and I don't care it is for C or C++ ( nothing except printf) ... My point only I have amakefile and I need to ignore some time some lines and some time I need it ... I need to make it as option ... how can I make it.

I couldn't pring the original example because it is long and difficult .

TK.
0
 

Author Comment

by:albusaidi
ID: 12201407

that mean I wnat to use condition ... because these lines can be in diffrent line ... any time I want to ignore any line I only make a condition ..
How can I do that ...
T.K again
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LVL 1

Expert Comment

by:gseidman
ID: 12201432

foo:
ifeq ($(kw), y)
      line1
else
      line2
endif
0
 

Author Comment

by:albusaidi
ID: 12202049
I tried Your code but still all the time the compiler execute both lines even if the condtion True or false.
0
 
LVL 1

Expert Comment

by:gseidman
ID: 12202109
Post exactly what you put in the Makefile and what you typed on the commandline.
0
 

Author Comment

by:albusaidi
ID: 12202165
foo:
      #ifeq ($(kw),y)
      $(CC) -o  1.o 1.cpp
      #else
      $(CC) -o  2.o 2.cpp
      #endif
make kw=y
OR
foo:
      i#feq ("$(kw)","y")
      $(CC) -o  1.o 1.cpp
      #else
      $(CC) -o  2.o 2.cpp
      #endif
make kw=y
0
 
LVL 1

Accepted Solution

by:
gseidman earned 50 total points
ID: 12202397
The problem is that you are putting in a # which is the comment character. You are commenting out the conditionals. That's not what I had in my example.
0
 

Author Comment

by:albusaidi
ID: 12202420
myt compiler is not except this (cygwin)
alway I get this message
$ make kw=y
ifeq ("y","y")
Syntax error: word unexpected (expecting ")")
make: *** [foo] Error 2

0
 

Author Comment

by:albusaidi
ID: 12211101
I got the way .. TK for every body

CC=gcc
foo:      
ifeq ('$(kw)','y')        // here we use '
      $(CC) -o  1.o 1.cpp // must be space
else
      $(CC) -o  2.o 2.cpp // must be space
endif

maybe it seem is easy but I spend more than 3 days on this example ... TK
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Expert Comment

by:gseidman
ID: 12211528
Please remember to assign points.
0

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