Link to home
Start Free TrialLog in
Avatar of bcsinnovations
bcsinnovations

asked on

Tcl/Tk scripting for VHDL models

Hello,
     I need one or two examples in tcl/tk scripting for testing vhdl model.The model can be a halfadder,multiplexer or any small sequential circuits.Can anyone help me.
Avatar of lombardp
lombardp

As far as I know, usually a VHDL model is tested through a VHDL test bench, and test is performed through a simulation tool that can be controlled using tcl/tk scripts.

Could you explain better what do you exactly need?

Avatar of bcsinnovations

ASKER

I am working with Modelsim and using test benchs for testing.I am following structural modelling technique.So whenever I make small changes in the VHDL Coding in lower level modules,I have to recompile all the files right from that lower module to the toplevel module and load the toplevel testbench and verify my output as waveforms.Is there any way to perform all these actions(compiling from lower module to top module,loading) by writing a tcl/tk script so that it will command  modelsim to do all actions mentioned above.
I think I have explained you better.
ASKER CERTIFIED SOLUTION
Avatar of lombardp
lombardp

Link to home
membership
This solution is only available to members.
To access this solution, you must be a member of Experts Exchange.
Start Free Trial