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Tcl/Tk scripting for VHDL models
Hello,
I need one or two examples in tcl/tk scripting for testing vhdl model.The model can be a halfadder,multiplexer or any small sequential circuits.Can anyone help me.
I need one or two examples in tcl/tk scripting for testing vhdl model.The model can be a halfadder,multiplexer or any small sequential circuits.Can anyone help me.
ASKER
I am working with Modelsim and using test benchs for testing.I am following structural modelling technique.So whenever I make small changes in the VHDL Coding in lower level modules,I have to recompile all the files right from that lower module to the toplevel module and load the toplevel testbench and verify my output as waveforms.Is there any way to perform all these actions(compiling from lower module to top module,loading) by writing a tcl/tk script so that it will command modelsim to do all actions mentioned above.
I think I have explained you better.
I think I have explained you better.
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Could you explain better what do you exactly need?