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Tcl/Tk scripting for VHDL models

Posted on 2004-10-26
Medium Priority
Last Modified: 2013-12-10
     I need one or two examples in tcl/tk scripting for testing vhdl model.The model can be a halfadder,multiplexer or any small sequential circuits.Can anyone help me.
Question by:bcsinnovations
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Expert Comment

ID: 12418913
As far as I know, usually a VHDL model is tested through a VHDL test bench, and test is performed through a simulation tool that can be controlled using tcl/tk scripts.

Could you explain better what do you exactly need?


Author Comment

ID: 12420772
I am working with Modelsim and using test benchs for testing.I am following structural modelling technique.So whenever I make small changes in the VHDL Coding in lower level modules,I have to recompile all the files right from that lower module to the toplevel module and load the toplevel testbench and verify my output as waveforms.Is there any way to perform all these actions(compiling from lower module to top module,loading) by writing a tcl/tk script so that it will command  modelsim to do all actions mentioned above.
I think I have explained you better.

Accepted Solution

lombardp earned 375 total points
ID: 12421040
Ok, first of all you have to execute a simulation. In the wave window, after you configured everything, save the format of the window and signals in "wave.do" file (it is the fastest way to write the wave.do file).

Create a macro file "mymacro.do" containing:

quit -sim
vcom file1.vhd
vcom file2.vhd
vcom file3.vhd
vcom top.vhd
vcom testbench.vhd
vsim work.testbench
view wave
do wave.do
run -all

Then in Modelsim console execute the macro with the following command:

do mymacro.do

Maybe you would need to customize further the script...

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