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CPLD Vs FPGA

Hi Everyone,

I am a newbie to the field of FPGAa nd CPLDS. I am intrested in studying the possibility of designing an MP3 Player on FPGA.

I have found that the experiments have been done to design MP3 player using CPLDs in the past but not FPGAs. Why is that ?

Are there any design references using FPGAs ?

Please also let me know the factors too conside while using FPGAsr.


Cheers,
Vpool
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vpool
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vpool
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1 Solution
 
d-glitchCommented:


Here is my answer to a previous similar question:  

      http://www.experts-exchange.com/Hardware/Microchips/Q_21680601.html

Microcontrollers are inexpensive and powerful.  They are also very slow.
The fastest PIC runs with a 40 MHz clock.
You would probably use a microcontroller for your a-b-c projects above.

FPGA's are more expensive and also very powerful.  Thye can be blazingly fast.
They can also be very complicated.  
Development tools for FPGA's can cost $50k.
A large FPGA project might take several manyears of effort.
You could probably use an FPGA for a complicated DSP project like your camera project [e] above.

You should also be aware of another type of chip:  the CPLD.
A CPLD is sort of like a small FPGA.
It is inexpensive and fairly fast.
The development tools are usually free.
CPLD's are great for timers and sequencers, glue logic, and simple DSP tasks like digital integrators.

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d-glitchCommented:
And another earlier and similar question:

      http://www.experts-exchange.com/Hardware/Microchips/Q_21279573.html

The marcocells in CPLD's are typically arranged as registered logic.  Each macrocell might have a flipflop, fed by a 5-input OR gate, fed by five 50 input AND gates.
You program the device by making real connections in the logic.  

In FPGA's the macrocells are typically flipflops fed by look-up tables.  In order to make a 50-input AND gate (an intrinsic function in a CPLD) you would need to cscade lots of look-up tables.  This can make the timing in  FPGA's more difficult to predict.  So simulation and optimization tend to be more critical.  Programming is also different.  You have to program the signal connections, and you also have to load all the look-up tables.  This is why some FPGA's need large external configuration memories that have to be loaded every time you power the chip up.

FPGA's have enormous capability, but it comes with a lot of baggage.
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d-glitchCommented:
I don't you could build much of an MP3 player in a CPLD ore even several CPLD's/
Where are you getting the files from?  
Who is going to handle the file access and decompression?

I expect you will need an FPGA and a fairly powerful microprocessor.

If you use an FPGA, you can build in the microprocessor.  
But then the develpment time is up in the man-years.
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vpoolAuthor Commented:
Thanks for the replies d_glitch

please refer to the following link....

http://www.xilinx.com/bvdocs/appnotes/xapp328.pdf

This what I am using as a reference...pdf has the link for the VHDl Source and test benches. I want to simulate-replicate this design using Altera Quartus II software ( Free ! ) on FPGA .

Isnt it possible to do that using quartus II ?

Please reply...

Vpool

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d-glitchCommented:
The Xilinx MP3 Player uses a 256-macrocell CPLD for control, interface, and glue logic.
This is a medium-large CPLD.  A small FPGA would certainly provide the same or greater capabilitly.

Note that this design has some limitations:

            It uses the PC parallel port rather than a USB port.
            It has not been built and tested, only simulated.
            The VHDL code is available, but the PC host software does not appear to be.

You can certainly download the VHDL file and get it to compile for an Altera FPGA.
That would be a useful exercise, and it should certainly be the first step, because you can do it for free.

But if you really want to build an MP3 play, you would still have months of work and hundreds of dollars of expenses ahead of you.  
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vpoolAuthor Commented:
Is it going to be possible to simulate the overall design  using Quartus ?
I am not worrying about the actual hardware implementation...It will be good if I can simulate the design on Altera...
Are there any complications in that ?

Please give your comments ?
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vpoolAuthor Commented:

And future work as you have said would require hundreds of dollars...Please let me know what sort of expenses  will be there ?

Thanks,
Vipul
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d-glitchCommented:
The major expenses will be the custom PC board ($100) and the tools for surface mount soldering (at lest 200).  The FPGA, the MP3 chip, and the DAC are all fine-pitch surface mount components.  You can not handle them relably without special equipment.  

Also the MP3 and DAC chips from Micronas appear to be obsolete, and may be hard to find.

I haven't used the Altera Quartus software.  But as I said, a design that fits in a 256-macrocell CPLD should fit easily into a small FPGA.  If you want to convert the Xilinx CPLDdesign to an Altera FPGA and simulate it you should be fine.

But what you will be simulating are a  parallel port interface, an I²C interface, and a flash memory interface.
All the MP3 functionality is in the MAS3507.
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