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verilog RAM testbench

Posted on 2006-06-26
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Last Modified: 2011-09-20
Hi

I found the below verilog RAM code on this website:

http://www.asic-world.com/examples/verilog/ram_sp_sr_sw.html#Single_Port_RAM_Synchronous_Read/Write

Could someone tell me how to write the testbench for this Single Port Synchronous Read/Write RAM ?

I want to print out the addresses and the values as they get written and read.

thanks.

1  //===========================================
2 // Function : Synchronous read write RAM  
3 // Coder : Deepak Kumar Tala
4 // Date : 18-April-2002
5 //===========================================
6 module ram_sp_sr_sw (
7 clk , // Clock Input
8 address , // Address Input
9 data , // Data bi-directional
10 cs , // Chip Select
11 we , // Write Enable/Read Enable
12 oe // Output Enable
13 );  
14  
15 parameter DATA_WIDTH = 8 ;
16 parameter ADDR_WIDTH = 8 ;
17 parameter RAM_DEPTH = 1 << ADDR_WIDTH;
18  
19 //--------------Input Ports-----------------------  
20 input clk ;
21 input [ADDR_WIDTH-1:0] address ;
22 input cs ;
23 input we ;
24 input oe ;  
25  
26 //--------------Inout Ports-----------------------  
27 inout [DATA_WIDTH-1:0] data ;
28  
29 //--------------Internal variables----------------  
30 reg [DATA_WIDTH-1:0] data_out ;
31 reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
32  
33 //--------------Code Starts Here------------------  
34  
35 // Tri-State Buffer control  
36 // output : When we = 0, oe = 1, cs = 1
37 assign data = (cs && oe && !we) ? data_out : 8'bz;  
38  
39 // Memory Write Block  
40 // Write Operation : When we = 1, cs = 1
41 always @ (posedge clk)
42 begin : MEM_WRITE
43   if ( cs && we ) begin
44     mem[address] = data;
45   end
46 end
47  
48 // Memory Read Block  
49 // Read Operation : When we = 0, oe = 1, cs = 1
50 always @ (posedge clk)
51 begin : MEM_READ
52   if (cs && !we && oe) begin
53     data_out = mem[address];
54   end
55 end
56  
57 endmodule // End of Module ram_sp_sr_sw
0
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Question by:boardergirl
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5 Comments
 
LVL 27

Expert Comment

by:d-glitch
ID: 17000269
Hello boardergirl,

This is a great place to get help with computers and softwareand lots of other stuff,
but there doesn't seem to be much traffic or experience with Verilog or VHDL.

If you search the EE Archives for Verilog, you only come up with about 40 questions.  
Three of them are yours.  Only a few of the others are as technical as yours.
Only one or two of the technical questions were answered satisfactorally.

                    http://search.experts-exchange.com/search.jsp?query=verilog

I have a lot of experience programming CPLD's with CUPL.
But I haven't done anything with FPGA's, ASIC's, or Verilog yet.

Sorry I can't be more help.
0
 
LVL 1

Accepted Solution

by:
hykes earned 250 total points
ID: 17039592
it's very simple.

instantiat the RAM instance ram_sp_sr_sw, provide clk, cs; then create a bus for address, a bus for write data and a bus for read data in your testbench. Hook them up and set the we, oe bits to write or read data.

Same time, at the clock event, check cs, we and oe signals. If they are valid, print the value of these address and data bus.

let me know if u need more help
0
 
LVL 27

Expert Comment

by:d-glitch
ID: 17227849
I don't think I should get any points on this one.

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