actually it should be a 7-to-128 bit decoder, since 2^7 = 128 ... i.e. with 7 bits you can obtain 128 different bit patterns.

A gate level description of such a decoder could be given with a Hardware Description Language, such as Verilog HDL or VHDL, for example using verilog:

wire [6:0] a; // this is the encoded input

wire [127:0] decoded_output; // this is the decoded output

// The decoded output line #0 is 1 if input is 0000000

assign decoded_output[0] = !a[7] & !a[6] & !a[5] & !a[4] & !a[3] & !a[2] & !a[1] & !a[0];

// The decoded output line #1 is 1 if input is 0000001

assign decoded_output[1] = !a[7] & !a[6] & !a[5] & !a[4] & !a[3] & !a[2] & !a[1] & a[0];

....

// The decoded output line #127 is 1 if input is 1111111

assign decoded_output[1] = a[7] & a[6] & a[5] & a[4] & a[3] & a[2] & a[1] & a[0];

(there is a more compact way to write the decoder, without explicitly write down a row for each output)

If you want the graphical representation of the decoder, you have only yo substitute the NOT operator (!) in the above equation with a NOT gate, and the AND operator (&) with a AND gate.

Let me know if I have understood your question