# Decoder

How do make a 8 to 128 bit decoder at gate level?
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Commented:
Hi  rgdicoch,
actually it should be a 7-to-128 bit decoder, since 2^7 = 128 ... i.e. with 7 bits you can obtain 128 different  bit patterns.

A gate level description of such a decoder could be given with a Hardware Description Language, such as Verilog HDL or VHDL, for example using verilog:

wire [6:0] a;                              // this is the encoded input
wire [127:0] decoded_output;     // this is the decoded output

// The decoded output line #0 is 1 if input is 0000000
assign decoded_output[0] = !a[7] & !a[6] & !a[5] & !a[4] & !a[3] & !a[2] & !a[1] & !a[0];

// The decoded output line #1 is 1 if input is 0000001
assign decoded_output[1] = !a[7] & !a[6] & !a[5] & !a[4] & !a[3] & !a[2] & !a[1] & a[0];

....

// The decoded output line #127 is 1 if input is 1111111
assign decoded_output[1] = a[7] & a[6] & a[5] & a[4] & a[3] & a[2] & a[1] & a[0];

(there is a more compact way to write the decoder, without explicitly write down a row for each output)

If you want the graphical representation of the decoder, you have only yo substitute the NOT operator (!) in the above equation with a NOT gate, and the AND operator (&) with a AND gate.

Let me know if I have understood your question

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Author Commented:
Lombardp,

Thanks for your response...yes this is exactly what I was looking for.  The 8 to 128 part was really 8 to 256... but I am only representing 128 different charcaters so that leaves me an extra input bit.  The input is fixed at 8 bits.  We are trying to implement the AES algorithm where processing is done 8 bits at a time...hence the 8 bits of input.  We are then taking those 8 bits and coming up with the ASCII character....and there are only 128 chars that we are interested in. Hope this makes sense.  But we are doing this at transisor level...custom layout.  But I wanted a "NAND GATE" representation of the decoder...that way I know internally what Im dealing with.  Thanks so much

Rigo
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Commented:
Ok, the above logical equations still remain valid. What you need is a way to express boolean operator with a proper combination of NAND gates.

First of all, a NAND is a NOT AND, so if I write c = NAND (a,b) = NOT (a AND b)

a NOT operator can be obtained with a NAND, using the same input value for both the NAND input.

b = NOT a = NOT (a AND a) = NAND(a,a)

so replace NOT operators with the NAND connected as above

a AND operator can be obtained with a NAND and a NOT, so

c = AND(a,b) = NOT NAND(a,b) = NAND( NAND(a,b) , NAND(a,b) )

a OR operator can be obtained with the following:

c = OR(a,b) = NOT ( AND(NOT a, NOT b) ) = (replace AND and NOT operators with the above NAND-based espressions)

Now you have the NAND equivalent expression for every boolean operator (AND, OR, NOT), so you can virtually express any boolean equation in terms of NANDs. Actually this work is performed by the so-called "logic synthsizer", a software that "maps" general boolean equations onto the "physical" operators of your technology (NAND gate in your case). The synthesizer performs also a sort of "reduction" of the final net, in order to minimize the number of gates used.

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Commented:
I might be misunderstanding (I don't know AES), but it sounds to me like you just want a special-purpose 256x8 ROM.  Implementing decoders and such is probably overkill.
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