g++ (or gcc in general) cooperates with make using -M. -M implies -E, which causes compilation to stop after the preprocessor stage. -M causes the C preprocessor to output a dependency rule suitable for make, instead of outputting preprocessed C source. You do this in a separate invocation of gcc with all the -I and -D args you would give to the main compile, but with -M also.
-MP and -MT are variants of the basic -M option. For understanding what happens, you want to get to grips with -M first.
For a good explanation of how to use -M, at the command line type:-
   info make Rules Auto
I suggest you try building a Makefile following the instructions to generate the .d makefiles. Experiment with -M or -MM, then maybe -MP. See if you can find a use for -MT. As always, post any further questions

You do have info installed don't you? I could post that section for you if not

I test g++ command with -M, -MT and -MP options, and they output the make rules. Your word made me able to understand part of the man page.

> You do this in a separate invocation of gcc with all the -I and -D args you would give to the main compile, but with -M
> also.
Do you mean an invocation separated from the one that really generate the binary? For example:
g++ -M -MT testprog.Po testprog.cc  &&  g++ -c -o testprog.o testprog.cc
What -M generates is the content of .deps/*.Po file, right?
I did a test for this:
************************************************************
Sui@walker ~/test
$ g++ -c -o testprog.o -M testprog.cc

Sui@walker ~/test
$ cat testprog.o
testprog.o: testprog.cc \
  /usr/lib/gcc/i686-pc-cygwin/3.4.4/include/c++/iostream \
  /usr/lib/gcc/i686-pc-cygwin/3.4.4/include/c++/i686-pc-cygwin/bits/c++config.h \
  /usr/lib/gcc/i686-pc-cygwin/3.4.4/include/c++/i686-pc-cygwin/bits/os_defines.h \
......
************************************************************
Is this why -M needs to be use seperately, because g++/gcc using -M cannot generate binary at the same time?

On another hand, here is a g++ invocation I obtain using "make -n" previously, because it have -c -o and -M -MT options at the same time, seems it is trying to make dependency files and binary at the same invocation, how can this happen?
********************************************************************
g++ -DPACKAGE_NAME=\"\" -DPACKAGE_TARNAME=\"\" -DPACKAGE_VERSION=\"\" -DPACKA
GE_STRING=\"\" -DPACKAGE_BUGREPORT=\"\" -DPACKAGE=\"MINKSUM\" -DVERSION=\"0.13.2
\" -DSTDC_HEADERS=1  -I. -I. -I../lib-src-reg -I../wrap-gmp-gcc3  -I../external/
include -I/usr/local/include -DVERBOSE -DGMPRATIONAL -ftemplate-depth-35 -g  -O2
  -Wall -W -march=prescott -mmmx -msse -msse2 -msse3 -pipe -O3 -MT LPinter.o -MD
 -MP -MF ".deps/LPinter.Tpo" \
          -c -o LPinter.o `test -f 'LPinter.cc' || echo './'`LPinter.cc; \
********************************************************************

I tried "info make Rules Auto" command, here is all the output:
***********************************************************************************
File: texinfo,  Node: Invoking makeinfo,  Next: makeinfo options,  Prev: makeinfo advantages,  Up: Creating an Info File
21.1.2 Running `makeinfo' from a Shell
--------------------------------------
To create an Info file from a Texinfo file, invoke `makeinfo' followed by the name of the Texinfo file.  Thus, to create the Info file forBison, type the following to the shell:
     makeinfo bison.texinfo
  (You can run a shell inside Emacs by typing `M-x shell'.)
  `makeinfo' has many options to control its actions and output; see the next section.
-----Info: (texinfo)Invoking makeinfo, 17 lines --All-- Subfile: texinfo-2------
***********************************************************************************
Hence, I have the input program, but couldn't get any instructions to generate the .d makefiles. Is it easy to install the thing correctly in cygwin? or you can copy the related information then I can read it?

Thank you very much for your kind help!

In my /usr/info directory, I have make.info.gz and make.info-1.gz through make.info-11.gz (your directory may be /usr/share/info). Worth installing if you don't have them.
Yes the compile line generates dependencies *and* a .o file. From "info gcc" (which is the complete manual for gcc, unlike the man page):

`-MD'
     `-MD' is equivalent to `-M -MF FILE', except that `-E' is not
     implied.  The driver determines FILE based on whether an `-o'
     option is given.  If it is, the driver uses its argument but with
     a suffix of `.d', otherwise it take the basename of the input file
     and applies a `.d' suffix.

     If `-MD' is used in conjunction with `-E', any `-o' switch is
     understood to specify the dependency output file (but *note -MF:
     dashMF.), but if used without `-E', each `-o' is understood to
     specify a target object file.

     Since `-E' is not implied, `-MD' can be used to generate a
     dependency output file as a side-effect of the compilation process.



`-MF FILE'
     When used with `-M' or `-MM', specifies a file to write the
     dependencies to.  If no `-MF' switch is given the preprocessor
     sends the rules to the same place it would have sent preprocessed
     output.

     When used with the driver options `-MD' or `-MMD', `-MF' overrides
     the default dependency output file.

So you see, for in_depth documentation of make and g++ / gcc, you really need the info files. Possibly you have them, but you need to set your INFOPATH. Anyway, the snippets above describe what's happening.
The "if" shell stmt you asked about earlier makes more sense to me now - as well as doing a compile it was making a new Test dependency file which was only adopted if the compile was successful. Or at least I think it was - you should be able to check that now.
You should have no especial trouble installing info files in cygwin.

Thank you! I roughly understand what is happen between make and g++/gcc. it is usually like: the Makefile first call g++/gcc to generate dependency files; then in later step the Makefile "include" the depedency files it just generated; then g++/gcc again to make the binary. This whole process is done without modifying Makefile stored in harddisk.

There is one detail I couldn't get in the pattern rule:
************************************************
              $(CC) -M $(CPPFLAGS) $< > $@.$$$$; \
              sed 's,\($*\)\.o[ :]*,\1.o $@ : ,g' < $@.$$$$ > $@; \
              rm -f $@.$$$$
************************************************
What does "$@.$$$$" mean here? I tried to google, but couldn't find.

Thank you very much!

Let's say:
  CC=gcc
  CPPFLAGS=-I../include
Consider main.c:-
Line 1 expands to:
   gcc -M I../include main.c > main.d.$$
Line 2 expands to:
   sed 's,\(main\)\.o[ :]*,\1.o main.d : ,g' < main.d.$$ > main.d
   Here, the \1 expands to main (1st parenthesised string)
Line 3 expands to:
  rm -f main.d.$$

I.e. main.d.$$ (the actual compiler output) is a temporary file used to make the eventual dependency file. As above:

   The purpose of the `sed' command is to translate (for example):

     main.o : main.c defs.h

into:

     main.o main.d : main.c defs.h
 $@, $* & $< are automatic variables: $$ expands (contracts) to literal $

In case you don't have "info make" yet, here is the topic describing Automatic Variables:-

File: make.info,  Node: Automatic,  Next: Pattern Match,  Prev: Pattern Examples,  Up: Pattern Rules

Automatic Variables
-------------------

   Suppose you are writing a pattern rule to compile a `.c' file into a
`.o' file: how do you write the `cc' command so that it operates on the
right source file name?  You cannot write the name in the command,
because the name is different each time the implicit rule is applied.

   What you do is use a special feature of `make', the "automatic
variables".  These variables have values computed afresh for each rule
that is executed, based on the target and prerequisites of the rule.
In this example, you would use `$@' for the object file name and `$<'
for the source file name.

   Here is a table of automatic variables:

`$@'
     The file name of the target of the rule.  If the target is an
     archive member, then `$@' is the name of the archive file.  In a
     pattern rule that has multiple targets (*note Introduction to
     Pattern Rules: Pattern Intro.), `$@' is the name of whichever
     target caused the rule's commands to be run.

`$%'
     The target member name, when the target is an archive member.
     *Note Archives::.  For example, if the target is `foo.a(bar.o)'
     then `$%' is `bar.o' and `$@' is `foo.a'.  `$%' is empty when the
     target is not an archive member.

`$<'
     The name of the first prerequisite.  If the target got its
     commands from an implicit rule, this will be the first
     prerequisite added by the implicit rule (*note Implicit Rules::).

`$?'
     The names of all the prerequisites that are newer than the target,
     with spaces between them.  For prerequisites which are archive
     members, only the member named is used (*note Archives::).

`$^'
     The names of all the prerequisites, with spaces between them.  For
     prerequisites which are archive members, only the member named is
     used (*note Archives::).  A target has only one prerequisite on
     each other file it depends on, no matter how many times each file
     is listed as a prerequisite.  So if you list a prerequisite more
     than once for a target, the value of `$^' contains just one copy
     of the name.

`$+'
     This is like `$^', but prerequisites listed more than once are
     duplicated in the order they were listed in the makefile.  This is
     primarily useful for use in linking commands where it is
     meaningful to repeat library file names in a particular order.

`$*'
     The stem with which an implicit rule matches (*note How Patterns
     Match: Pattern Match.).  If the target is `dir/a.foo.b' and the
     target pattern is `a.%.b' then the stem is `dir/foo'.  The stem is
     useful for constructing names of related files.

     In a static pattern rule, the stem is part of the file name that
     matched the `%' in the target pattern.

     In an explicit rule, there is no stem; so `$*' cannot be determined
     in that way.  Instead, if the target name ends with a recognized
     suffix (*note Old-Fashioned Suffix Rules: Suffix Rules.), `$*' is
     set to the target name minus the suffix.  For example, if the
     target name is `foo.c', then `$*' is set to `foo', since `.c' is a
     suffix.  GNU `make' does this bizarre thing only for compatibility
     with other implementations of `make'.  You should generally avoid
     using `$*' except in implicit rules or static pattern rules.

     If the target name in an explicit rule does not end with a
     recognized suffix, `$*' is set to the empty string for that rule.

   `$?' is useful even in explicit rules when you wish to operate on
only the prerequisites that have changed.  For example, suppose that an
archive named `lib' is supposed to contain copies of several object
files.  This rule copies just the changed object files into the archive:

     lib: foo.o bar.o lose.o win.o
             ar r lib $?

   Of the variables listed above, four have values that are single file
names, and three have values that are lists of file names.  These seven
have variants that get just the file's directory name or just the file
name within the directory.  The variant variables' names are formed by
appending `D' or `F', respectively.  These variants are semi-obsolete
in GNU `make' since the functions `dir' and `notdir' can be used to get
a similar effect (*note Functions for File Names: File Name
Functions.).  Note, however, that the `D' variants all omit the
trailing slash which always appears in the output of the `dir'
function.  Here is a table of the variants:

`$(@D)'
     The directory part of the file name of the target, with the
     trailing slash removed.  If the value of `$@' is `dir/foo.o' then
     `$(@D)' is `dir'.  This value is `.' if `$@' does not contain a
     slash.

`$(@F)'
     The file-within-directory part of the file name of the target.  If
     the value of `$@' is `dir/foo.o' then `$(@F)' is `foo.o'.  `$(@F)'
     is equivalent to `$(notdir $@)'.

`$(*D)'
`$(*F)'
     The directory part and the file-within-directory part of the stem;
     `dir' and `foo' in this example.

`$(%D)'
`$(%F)'
     The directory part and the file-within-directory part of the target
     archive member name.  This makes sense only for archive member
     targets of the form `ARCHIVE(MEMBER)' and is useful only when
     MEMBER may contain a directory name.  (*Note Archive Members as
     Targets: Archive Members.)

`$(<D)'
`$(<F)'
     The directory part and the file-within-directory part of the first
     prerequisite.

`$(^D)'
`$(^F)'
     Lists of the directory parts and the file-within-directory parts
     of all prerequisites.

`$(+D)'
`$(+F)'
     Lists of the directory parts and the file-within-directory parts
     of all prerequisites, including multiple instances of duplicated
     prerequisites.

`$(?D)'
`$(?F)'
     Lists of the directory parts and the file-within-directory parts of
     all prerequisites that are newer than the target.

   Note that we use a special stylistic convention when we talk about
these automatic variables; we write "the value of `$<'", rather than
"the variable `<'" as we would write for ordinary variables such as
`objects' and `CFLAGS'.  We think this convention looks more natural in
this special case.  Please do not assume it has a deep significance;
`$<' refers to the variable named `<' just as `$(CFLAGS)' refers to the
variable named `CFLAGS'.  You could just as well use `$(<)' in place of
`$<'.

   GNU `make' provides support for the SysV `make' feature that allows
special variable references `$$@', `$$(@D)', and `$$(@F)' (note the
required double-"$"!) to appear with the _prerequisites list_ (normal
automatic variables are available only within a command script).  When
appearing in a prerequisites list, these variables are expanded to the
name of the target, the directory component of the target, and the file
component of the target, respectively.

   Note that these variables are available only within explicit and
static pattern (*note Static Pattern Rules: Static Pattern.) rules;
they have no special significance within implicit (suffix or pattern)
rules.  Also note that while SysV `make' actually expands its entire
prerequisite list _twice_, GNU `make' does not behave this way: instead
it simply expands these special variables without re-expanding any
other part of the prerequisites list.

   This somewhat bizarre feature is included only to provide some
compatibility with SysV makefiles.  In a native GNU `make' file there
are other ways to accomplish the same results.  This feature is
disabled if the special pseudo target `.POSIX' is defined.