I have some ideas for skipping TCP in a high level application, but first things first - right now I just want to take the "Ethernet MAC 10/100 Mbps" core (http://www.opencores.com/projects.cgi/web/ethmac
) and connect it to a regular PC.
I have the following Altera FPGA:
It's my understanding that a PHY chip is needed that ultimately interfaces with a female RJ-45 connector.
I'm guessing that the "wishbone" interface from the Ethernet core will ultimately be wired to a male PCI interface? Conceptually how does this work? I tried to read the wikipedia entry on wishbone and it sounds like greek to me (my background is VHDL and then higher level languages). I also read somewhere that the Altera's Avalon bus can be used?
At first I thought this was going to be easy.. I though I could just wire 32 of the FPGA's output pins to the 32 PCI pins.. wishful thinking :)