# Why do ram DIMMs always have an amount of memory that is a powers of two?

Hello,

I've often wondered why it is that DIMMs of RAM invariably have an amount of memory which is a power of two. Why? What aspect of modern computer architectures necessitates this?

Thanks,
Sternocera
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1) Theoretically it is possible to create modules of RAM for example 192 Mb which might work on most systems. The idea is the some of DIMMs have 2 banks(mostly biggest ones, 2 virtual DIMMs in 1 DIMM circuit board), all current 2-bank modules have banks of the same size, but it is possible to create DIMM module which would have for example first bank of 128Mb and second one 64 or 32.

Chipsets should be able to handle several banks with different sizes (no matter if they are on the different DIMMs or the same ones).

2) Size of 1 bank is still power of 2. That is to make easier memory address translation without complex computations. If chipset needs to fetch byte from memory from arbitrary memory location, it should determine memory bank, and address in the bank. If size of bank is power of 2 it is possible to implement that using only bit-shift operations, which are very fast and simple.

If bank size is not a power of 2, we would need to add summators/comparators, which are FAR slower and takes more transistors to implement.
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Commented:
a more complete answer :  the ram must be adressed, and is organised in rows and colums
(think of it as a square)
if you have 4 elements of ram, you situation is    :   4 elements = 2²
n      n    <--row 0
n      n    <--row 1
^      ^
|       |
column   0      1

if you want more, just ask !
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Commented:
Well, 3 rows 7 columns would produce 21 byte DIMM but this is not going to happen :-)

The question is why number of rows & columns is power of 2 :-)
That is for efficient memory controller implementation. It is possible to create custom memory controller which could handle non-power-of-2 rows/columns but this would significantly impact performance&cost.
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the why is answered in the adressing; the same bus carries the row and column signals, so it is much easier to keep them the same number.
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Author Commented:
"If size of bank is power of 2 it is possible to implement that using only bit-shift operations, which are very fast and simple."

How? A bitshift is only useful for doubling or halving a binary number, or finding powers of two; If we're looking for, say, a 32-bit integer that is fifth in an array of integers, for example, I can see no reason everything being a power of two helps us.

"the why is answered in the adressing; the same bus carries the row and column signals, so it is much easier to keep them the same number."

I am familiar with memory addresses; I am a C++ programmer. I have a fairly high level understanding of computer architecture; Could you clarify what you meant here? On most architectures, memory addressed are 32-bits, typically represented as hexadecimal, in the form 0x00000000 - 0xFFFFFFFF. What part of that number is the row, and what part is the column? I have an understanding of virtual address spaces versus physical address spaces, address resolution, the translation lookaside buffer and so on.

I'm probably missing something obvious here.

Regards,
Sternocera

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"virtual address spaces versus physical address spaces, address resolution, the translation lookaside buffer" - all these happens inside a processor and produces physical address.

Second step - get bank number (i.e. which DIMM or which part of it have this phisical address), and what row/column at dram to read - that is being done by memory controller (in chipset, or inside processor in AMD Athlon(754, 939 and 940 sockets) & Intel i7).

For example, 512Mb DIMM module usually have:
4 banks, 8192 rows of 16384 bits.

So if you want to know what is byte position of the requested byte, chipset would do the following simplified (pseudocode):

As you see all these operations could be done without divisions and modulo using bit operations.
(Simplification is that you read 64 bit at once or even 128 bit)

Why there are rows & columns, not just address index (i.e. if we want 512Mx8bit chip with linear addressing)?  Because that would require to have multiplexer with 512M contacts in hardware which would consume about 512M*log2(512M) transistors. Also it is slow.

If we go with rows & columns we need just 2 demultiplexors(with 8192 & 16384/8 contacts), one with 8192*log2(8192) transistors, second with 16384*log2(16384/8) transistors which require much less space & works much faster.

16384 is divided by 8 because each chip output 8 bits, not just any particual bit.

So with 2 bit bank, 13 bit row and 11 bit column you select 8 bit memory register. Total address width is 2+13+11 = 26, 2^26 = 64M 64-bit words which is 512Mb .
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Author Commented:
BarsMonster,

That's made it clearer. Thanks a lot,

Regards,
Sternocera
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