Implementing HyperTransport protocol on FPGAs

Hi,
I would like to know how to implement HyperTransport protocol on FPGA architecture (VHDL). Any implementation guidelines (any sort of resource) will be beneficial.

Thanks!
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Mc7400Commented:
Hello,

HyperTransport Protocol Architecture:
http://www.extremetech.com/article2/0,2845,1154814,00.asp

HyperTransport Technology I/O Link White paper pdf file:
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs
/HyperTransport_IO_Link_Whitepaper_25012A.pdf

HyperTransport consortium site:
http://www.hypertransport.org/default.cfm?page=Home
http://www.hypertransport.org/docs/uploads/HT_General_Overview.pdf

A HyperTransport Tunnel controller written in SystemC:
http://www.opencores.org/projects.cgi/web/ht_tunnel/overview

Implementing a HyperTransport protocol version 1.10 pdf file:
http://www.veriest-v.com/docs/HDL_vip/HDH1000.28.11.07.pdf

HyperTransport (HT) MegaCore Function for Altera FPGA:
http://www.altera.com/products/ip/iup/hypertransport/m-alt-hypertransport.html

Regards,

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