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Need help designing a BJT RLC Tuned Amplifier

I need help designing a BJT RLC tuned amplifier (tuned circuit in the collector) with the following specs:
Q = 10
Gain = 40 V/V
Rsource = 50 ohm
Rload = 4.7k ohm
Center Freq (fo) = 3.223MHz
Using a 2N3904 transistor

Ultimately, I need to simulate this circuit in PSpice.  Please any help is really appreciated.
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1 Solution
Here is a link to some general design considerations. It has a sample citcuit for a 2N3904. It is for audio but you can modify it for 3 MHz,
The r4 can be set at 50 ohms for you input resistance.
You can put a tunred circuit in the output with the appropriate values of L and C for 3 MHz.
This is a classic end-of-term project for a transistor circuits class.

There is enough information in the specs to design the RLC circuit.
Can you tell if you need a parallel or series configuration?

Next you have to pick the resistors to set the gain, and operating point.
Do you know how to do that?

Do you have the data sheet for the 3904?
Are you supposed to use the hybrid pi model?

Can you just plug values into PSpice and do trial and error?
Or do you have to present calculations?
bg18461Author Commented:
Aburr, thank you for the link, I am looking it over now.

d-glitch, actually you are correct it is a project for a class, but I have not taken the course yet.  I wanted to get a jump on this project as I have a little, albiet limited, knowledge of BJT's and the like.  This is where your tutolage will help.

As for your questions:  
- I am not sure if it needs to be in parallel or series configuration.
- I would like some direction on setting up the resistors.  If you could show me the circuit setup, I think I can use kvl,kcl,ohms to figure out the resistors.  If you can show me a better way, I would definitely appreciate it.
- I do not have the datasheet for the transistor.  What a friend did who took the class was to generate the circuit in PSPICE and it showed info on the trans such as beta, etc...
- The problem does not ask to use the hybrid pi model, but I am open to learning it if it simplifies the process, but from what I have read so far, I think it will complicate it...
- This problem does require calculations then showing the match in PSPICE, then finally building it by hand.

Please any guidance you can provide would be incredibly helpful, happy new year.
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bg18461Author Commented:
OK guys, help me a bit more with getting started, what should be my first step?
bg18461Author Commented:
Ok, in my reading these are some of the first steps to take.  I can determine my bandwidth (BW) by knowing my Qpoint and my cutoff frequency (fo).

BW=fo/Q, so BW=3.223MHz/10,

I can now determine my cutoff frequencies,
fc1=fo-(BW/2), fc1=3.223MHz-(322.3kHz/2)=3.06185MHz

fc2=fo+(BW/2), fc2=3.223MHz+(322.3kHz/2)=3.38415MHz

How do I determine my L and C?
If you want to get a jump on course, you should start at the beginning.

You can hope to tackle the final project without coving the earlier material.

Forget about the tuned amplifier for now.

Do you know how do design a common emitter amp with a gain of 40
with the specified input and output impedances?

If so, start there.  If not, give up.
>> You can't hope to tackle the final project without covering the earlier material.
If  bg18461  had followed the procedure outlined in aburr's first link, he could have completed the design in less than
an hour.

This is a homework/exam question, so we aren't allowed to post complete solutions.  But this question is well answered.
"Please any help is really appreciated"
he got lots of help.
See also d-glitch comment above.

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