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How to exchange signal from a ppc440 and ISE

Posted on 2010-09-09
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Last Modified: 2012-05-10
Hello,

I actually implemented a PPC440 inside my existing ISE(11.4) project and i would like to share some signals between my entire code in ISE and some code inside the PPC.

What i see in XPS is that i can input or output some signals from or to ISE if i map them with an address in the UCF.
But i don't want to output or input them, i just want a bus (not in the ucf) that can be share between my code in ISE(vhdl) and my code in the PPC(c).

I though it should be really simple, but i was not able to find anything on the net.

Thanks for your help.
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Question by:DBTechnique
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LVL 12

Expert Comment

by:HappyCactus
Comment Utility
I do not know if I did understand well your problem.
To "see" a signal from code, you must connect it to a system register. It doesn't matter if the processor is a phisical cpu or a softprocessor, you must have a register.
The simpler way to do this is realize an I/O mapped register.
You must connect the signal to an I/O pin of the cpu block, and pass his value through a memory mapped I/O.
Sorry I cannot be more precise or provide you some code: but I think you can find some example in the opencores.org website.
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by:DBTechnique
Comment Utility
i'm sorry for my bad explanation.
So if i understand, i should create a register (can you tell me what kind of register and how to create them please) connected to the ppc (does this register should be connected on a bus, plb or other ?).
I do that inside XPS.
Then in ISE i should be able to read or write this register(that must be in system.vhd) right ?

thank you for your answer cause i m really lost
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Expert Comment

by:HappyCactus
Comment Utility
First you must "export" the signal from the block / package of the PPC (is it an internal signal, right?).
Second, pass this signal through a flip-flop and read it through an address of the I/O map (I do not know if ppc has separate memory and I/O address space...)
sorry I cannot be more precise, since I do not know ISE and XPS
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by:DBTechnique
Comment Utility
To give you a better view, my purpose is to create a lan communication.

For that i have an example of echo server that i found, it works well, but now instead of echo the data back, i want to get data inside my vhdl code (inside ISE) in order to process them. i mean i want to output/input data from the top of the embeded processor (system.vhd) in order to use them in ISE.
But i don't want to output them from the FPGA, so no ucf address.

I think your idea of register is good, but it's just i don't understand how to create them

Hope this detail can help you to understand better my problem.
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Author Comment

by:DBTechnique
Comment Utility
ok thank you for your help, if you know some place where i can find tutorial to do that it will be perfect.
I understand the step you describe but i don't know how to do it.

thanks
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Expert Comment

by:HappyCactus
Comment Utility
I well understand your problem.
So this is the way: connect your device (the one that processes your data in the vhdl code) to the address space of the PPC. You can do this as usual in your vhdl code, when you connect different devices/controller to your ppc.
so you only have to modify your echo server to write to that address.
I do not know what kind of tool ISE provides for this, if it uses a graphical tool or simply a vhdl editor. Check some example of System On Chip.
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by:DBTechnique
Comment Utility
i give you some informations about tools :

i have ISE where i have a lot of vhdl code in order to do many different process. this code is on text editor mode with a top level module (and many other) that have input and output of the FPGA.

Inside ISE, i implemented an ipcore that is a PPC440. when i open this ipcore, it's open a soft called XPS that allow graphically the user to manage many things inside the PPC.

Using XPS, i have a PPC440, and other device that link to it (ethernet mac, rs232 etc...) since all these devices go out of the fpga they have some port.

after configuring my PPC inside XPS, i close it and want to use it inside ISE. So in my ISE i can instatiate as component my embedded PPC, but on the instatiation i have only the port of the previous device.
What i want is to have a new port directly connected to the PPC440 c code.

I think your idea of add a register as a device inside XPS is good like that i can have maybe a new port on my instantiation that i can use in ISE. But i don't know how to add register and where i can found register.
For you second solution (add a vhdl module inside XPS) it can work, but it's not what i want to do.

Sorry for this long explanation, hope it can help you
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Expert Comment

by:HappyCactus
Comment Utility
No, I meant this: fpga have many "blocks", the PPC block (with subblocks, eventually) and others like interfaces, devices, etc.
These devices are connected to the PPC through an address space mapping - usually just a multiplexer with some other control code. Perform your "processing block" outside the PPC block / ipcore (and xps), but (obviously) inside the fpga, with vhdl, verilog or other tools.
This way you preserve the ppc functionality and code!.
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by:DBTechnique
Comment Utility
yes it's what i want to do, but my problem is i don't know how to interface the ppc block with my vhdl code. Just before i found a way that i'm trying right know(i don't know yet if that work), say to use a block ram (dual port) one port is on the PLB bus and the other is usable by the vhdl part. it's like a register (a bit mor complex) but it seems usable.
i ll try this way first, if you have some advise or other comment i ll be pleased to ear it .

thank you a lot for your help
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Expert Comment

by:HappyCactus
Comment Utility
If you substitute the ram block with an 8 (or whatever) bit flipflop / latch, you have done it.
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by:DBTechnique
Comment Utility
thanks, but i can found dpram ip in xps, but not flipflop ip, so should i build it myself ? if yes  can you explain me how.

Else, i tryed with a DPRAM but unfortunately i'm not able to make it work.
i connected the port A of the DPRAM to a controller that is connected on the PLB bus,
Then i connected the port B of the DPRAM to an external port (in order to have it on my ISE).

after that i used this code to write data inside the DPRAM (by SDK)
*(volatile unsigned int*)(XPAR_XPS_BRAM_IF_CNTLR_1_BASEADDR) = 3;

I wanted to write 3 on the base address of the DPRAM, but nothing happen. Did i do something wrong ?
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Expert Comment

by:HappyCactus
Comment Utility
flipflop is a basic digital device that memorize a bit and make it available for reading. it's like a ram - but writing the flipflop is performed from a signal and a clock or write command. it's like a latch - but it's a synchronous device.
Since FF and latch are basic concept of digital electronics, I suggest you to look for a good vhdl and digital design book.
Anyway. A DFF can be implemented in VHDL like this:


library ieee;
USE ieee.std_logic_1164.all;

ENTITY dff IS
  PORT (d, clk : IN STD_LOGIC;
        q: BUFFER STD_LOGIC;
        notq: BUFFER STD_LOGIC;
  );
END dff;

ARCHITECTURE dff1 OF dff IS
BEGIN
  PROCESS(clk)
  BEGIN
    IF (clk'EVENT AND clk='1') THEN
      q <= d;
    END IF;
  END PROCESS;
  notq <= NOT q;
END dff1;

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by:DBTechnique
Comment Utility
thanks.
But actually my principal problem is to write the code in C to be able to write inside a fifo or a dpram or anything.
I understand the Vhdl but i'm not able to interface it with the PPC.

As i told before i tried to write inside my DPRAM (or i think it's same with a flipflop) with the line :
*(volatile unsigned int*)(XPAR_XPS_BRAM_IF_CNTLR_1_BASEADDR) = 3;
But it did not work.

I'm almost sure that this line is not good, but i can't figure out the right one. So imagine you have a DPRAM or a flipflop where the base address is Mydevice_baseadd, what should i write in C code in order to write inside it ? and read in a second time
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Expert Comment

by:HappyCactus
Comment Utility
your address should be XPAR_XPS_BRAM_IF_CNTLR_1_BASEADDR.
for example, if your address is 0x10000000, then

*(volatile unsigned int*)(0x10000000) = 3;

should make the work. But pay attention if you have a MMU in your device and O.S., because you need to have the permission to write to that page.
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Author Comment

by:DBTechnique
Comment Utility
ok so if i understand well, i have in the xparameter.h file a line :
#define XPAR_XPS_BRAM_IF_CNTLR_1_BASEADDR 0xFFFFC000

so if i write :
*(volatile unsigned int*)(XPAR_XPS_BRAM_IF_CNTLR_1_BASEADDR) = 3;
or
*(volatile unsigned int*)(0xFFFFC000) = 3;
it should work right ?

but you think it's enought, there is no special line to enable stuff, or to say the width of the data or the amount of data or write/read ?

Cause when i tried *(volatile unsigned int*)(XPAR_XPS_BRAM_IF_CNTLR_1_BASEADDR) = 3; it did nothing.
Moreover how can i check the MMU stuf that you speak about ?

thanks
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Expert Comment

by:HappyCactus
Comment Utility
The size of write is defined by the type of the data you are using (unsigned int), to the implementation of this compiler (usually 32 bit) and the architecture (some cpu force 16 bit writings into 32 bits - but this should be transparent).
For the MMU, if you do not have the rights to write, your program should receive an exception.

About MMU, check if you are mapping logical address into different physical space.
How to map logical and physical spaces, depends on the Operating System you are using. If your firmware do not have an o.s., simply disable MMU and write directly into the physical space, or configure the MMU accordingly your needs.
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Author Comment

by:DBTechnique
Comment Utility
ok so i found out how to write and read inside a Dpram or other device :
                Xuint32 data;
            data = XIo_In32(XPAR_XPS_BRAM_IF_CNTLR_1_BASEADDR);
            xil_printf("\tread from BRAM : 0x%X\r\n",data);

            XIo_Out32(XPAR_XPS_BRAM_IF_CNTLR_1_BASEADDR,*((int*)p->payload));
            xil_printf("\twriting\r\n",data);

with this code i'm able to read and after write a new data, then reread etc... since playload is the input of my keyboard i can check that it's work well.

So i really happy, but as everytime after a problem solve a second occurs, now i would like to read the data that i put inside my DPRAM by ISE on the port B (i use the port A with the controller on XPS).

so now, i know that i have a known data on the DPRAM at the address 0 of th DPRAM, and the port B is external so i can map it in ISE.

i just wrote a small vhdl code in order to read the DPRAM like this:

begin
fpga_0_clk_1_sys_clk_pin => fpga_0_clk_1_sys_clk_pin,
fpga_0_rst_1_sys_rst_pin => fpga_0_rst_1_sys_rst_pin,
xps_bram_if_cntlr_1_bram_BRAM_Rst_B_pin => xps_bram_if_cntlr_1_bram_BRAM_Rst_B_pin_s,
xps_bram_if_cntlr_1_bram_BRAM_Clk_B_pin => xps_bram_if_cntlr_1_bram_BRAM_Clk_B_pin_s,
xps_bram_if_cntlr_1_bram_BRAM_EN_B_pin => xps_bram_if_cntlr_1_bram_BRAM_EN_B_pin_s,
xps_bram_if_cntlr_1_bram_BRAM_WEN_B_pin => xps_bram_if_cntlr_1_bram_BRAM_WEN_B_pin_s,
xps_bram_if_cntlr_1_bram_BRAM_Addr_B_pin => xps_bram_if_cntlr_1_bram_BRAM_Addr_B_pin_s,
xps_bram_if_cntlr_1_bram_BRAM_Dout_B_pin => xps_bram_if_cntlr_1_bram_BRAM_Dout_B_pin_s,
xps_bram_if_cntlr_1_bram_BRAM_Din_B_pin => xps_bram_if_cntlr_1_bram_BRAM_Din_B_pin_s
      );

process (fpga_0_clk_1_sys_clk_pin, fpga_0_rst_1_sys_rst_pin)      
begin
      if (fpga_0_rst_1_sys_rst_pin = '1') then
            xps_bram_if_cntlr_1_bram_BRAM_Rst_B_pin_s <= '1';
            xps_bram_if_cntlr_1_bram_BRAM_Addr_B_pin_s <= x"00000000";
      
      elsif (fpga_0_clk_1_sys_clk_pin'event and fpga_0_clk_1_sys_clk_pin = '1') then
            xps_bram_if_cntlr_1_bram_BRAM_Rst_B_pin_s <= '0';
            xps_bram_if_cntlr_1_bram_BRAM_Addr_B_pin_s <= x"00000000";
      
      end if;
end process;

xps_bram_if_cntlr_1_bram_BRAM_Clk_B_pin_s <= fpga_0_clk_1_sys_clk_pin;
xps_bram_if_cntlr_1_bram_BRAM_EN_B_pin_s <= '1';
xps_bram_if_cntlr_1_bram_BRAM_WEN_B_pin_s <= "0000";
xps_bram_if_cntlr_1_bram_BRAM_Din_B_pin_s <= x"00000000";

end Behavioral;

Unfortunately i'm not able to read my data on  xps_bram_if_cntlr_1_bram_BRAM_Dout_B_pin_s,   the output bus remain to the value 0. Do you have an idea?
begin
fpga_0_clk_1_sys_clk_pin => fpga_0_clk_1_sys_clk_pin,
fpga_0_rst_1_sys_rst_pin => fpga_0_rst_1_sys_rst_pin,
xps_bram_if_cntlr_1_bram_BRAM_Rst_B_pin => xps_bram_if_cntlr_1_bram_BRAM_Rst_B_pin_s,
xps_bram_if_cntlr_1_bram_BRAM_Clk_B_pin => xps_bram_if_cntlr_1_bram_BRAM_Clk_B_pin_s,
xps_bram_if_cntlr_1_bram_BRAM_EN_B_pin => xps_bram_if_cntlr_1_bram_BRAM_EN_B_pin_s,
xps_bram_if_cntlr_1_bram_BRAM_WEN_B_pin => xps_bram_if_cntlr_1_bram_BRAM_WEN_B_pin_s,
xps_bram_if_cntlr_1_bram_BRAM_Addr_B_pin => xps_bram_if_cntlr_1_bram_BRAM_Addr_B_pin_s,
xps_bram_if_cntlr_1_bram_BRAM_Dout_B_pin => xps_bram_if_cntlr_1_bram_BRAM_Dout_B_pin_s,
xps_bram_if_cntlr_1_bram_BRAM_Din_B_pin => xps_bram_if_cntlr_1_bram_BRAM_Din_B_pin_s
	);

process (fpga_0_clk_1_sys_clk_pin, fpga_0_rst_1_sys_rst_pin)	
begin
	if (fpga_0_rst_1_sys_rst_pin = '1') then
		xps_bram_if_cntlr_1_bram_BRAM_Rst_B_pin_s <= '1';
		xps_bram_if_cntlr_1_bram_BRAM_Addr_B_pin_s <= x"00000000";
	
	elsif (fpga_0_clk_1_sys_clk_pin'event and fpga_0_clk_1_sys_clk_pin = '1') then
		xps_bram_if_cntlr_1_bram_BRAM_Rst_B_pin_s <= '0';
		xps_bram_if_cntlr_1_bram_BRAM_Addr_B_pin_s <= x"00000000";
	
	end if;
end process;

xps_bram_if_cntlr_1_bram_BRAM_Clk_B_pin_s <= fpga_0_clk_1_sys_clk_pin;
xps_bram_if_cntlr_1_bram_BRAM_EN_B_pin_s <= '1';
xps_bram_if_cntlr_1_bram_BRAM_WEN_B_pin_s <= "0000";
xps_bram_if_cntlr_1_bram_BRAM_Din_B_pin_s <= x"00000000";

end Behavioral;

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Author Comment

by:DBTechnique
Comment Utility
to give you more informations, i was able to read and write from HW(ISE) by vhdl using the portB of the DPRAM, and i'm able to write and read from SW(XPS) by C code using the portA of the DPRAM.
But i'm not able to write on the portA and read on the portB for example.
Do you have an idea ?


ps: on the previous message the is an error on the code line 9 and 10:
Din_B_pin is Dout_B_pin_s
Dout_B_pin is Din_B_pin_s
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Author Comment

by:DBTechnique
Comment Utility
I still have problem to read and write my DPRAM.

In the PPC side, i'm able to read and write inside the DPRAM (port A) using this code
            XIo_Out32(XPAR_XPS_BRAM_IF_CNTLR_1_BASEADDR,*((int*)p->payload));          
            Xuint32 data;
            data = XIo_In32(XPAR_XPS_BRAM_IF_CNTLR_1_BASEADDR);
            xil_printf("\tread from BRAM : 0x%X\r\n",data);

In the ISE side i'm able to read and write on the DPRAM (portB)
           by reading and writing value at the address 0,1,2 of the DPRAM and check values in chipscope  
           pro.

But ican't write by port A and read by port B or inverse well.
if i write by port A, i get value on the port B with a very big lag and not at the address i want.
if i write by port B, i get values that wrote, but randomly on the same address...

I'm really confuse .... can you help me please
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Expert Comment

by:HappyCactus
Comment Utility
I do not know the IP you are using. Maybe that behavior is expected, maybe you are missing something. Check carefully the ip's documentation and see if there is some example.
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Author Comment

by:DBTechnique
Comment Utility
the IP i'm using in XPS are
- bram_block 1.00a for the memory block
- xps_bram_if_cntrl in order to link the portA of this DPRAM to the PLB bus of the PPC

The port B of this DPRAM is used as external, like that i can use it in ISE directly.

Of course i checked the documentation, but didn't find what i missed ....
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LVL 12

Expert Comment

by:HappyCactus
Comment Utility
I do not know how you connected the block, so it's difficult for me to tell what you are doing wrong.
You could try to exchange porta and portb, so to see if something changes. If it does, the problem is in the DPRAM.
But since you are expecting difficulty only with portA, it seems possible that the problem is to the link PORTA-PLB. Check carefully the connection and the requirements.
The problem could be also in the PLB bus.

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Author Comment

by:DBTechnique
Comment Utility
Sorry for my bad explanation, but i have the same difficulty on the both port
if i write and read on the portA it's ok
if i write and read on port B it's also ok
problem is to write on port A and read on port B or write on port B and read on port A

to better understand i join you my code :
- first part is in ISE => to read the port B of the DPRAM
- second part is in XPS => setup the port A and B of th DPRAM
- third part is in SDK => wrtie data (payload, data comming from keyborad) on the port A of the DPRAM
IN ISE


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity TOP is
	PORT(
		fpga_0_RS232_RX_pin : IN std_logic;
		fpga_0_DIP_Switches_4Bit_GPIO_IO_I_pin : IN std_logic_vector(0 to 3);
		fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0_pin : IN std_logic;
		fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin : IN std_logic_vector(7 downto 0);
		fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0_pin : IN std_logic;
		fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0_pin : IN std_logic;
		fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin : IN std_logic;
		fpga_0_clk_1_sys_clk_pin : IN std_logic;
		fpga_0_rst_1_sys_rst_pin : IN std_logic;    
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQ_pin : INOUT std_logic_vector(31 downto 0);
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQS_pin : INOUT std_logic_vector(3 downto 0);
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQS_N_pin : INOUT std_logic_vector(3 downto 0);
		fpga_0_Hard_Ethernet_MAC_MDIO_0_pin : INOUT std_logic;      
		fpga_0_RS232_TX_pin : OUT std_logic;
		fpga_0_LEDs_8Bit_GPIO_IO_O_pin : OUT std_logic_vector(0 to 7);
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_A_pin : OUT std_logic_vector(12 downto 0);
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_BA_pin : OUT std_logic_vector(1 downto 0);
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_RAS_N_pin : OUT std_logic;
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_CAS_N_pin : OUT std_logic;
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_WE_N_pin : OUT std_logic;
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_CS_N_pin : OUT std_logic;
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_ODT_pin : OUT std_logic;
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_CKE_pin : OUT std_logic;
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_DM_pin : OUT std_logic_vector(3 downto 0);
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_CK_pin : OUT std_logic_vector(1 downto 0);
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_CK_N_pin : OUT std_logic_vector(1 downto 0);
		fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin : OUT std_logic;
		fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin : OUT std_logic_vector(7 downto 0);
		fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0_pin : OUT std_logic;
		fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0_pin : OUT std_logic;
		fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0_pin : OUT std_logic;
		fpga_0_Hard_Ethernet_MAC_MDC_0_pin : OUT std_logic;
		fpga_0_Hard_Ethernet_MAC_PHY_MII_INT_pin : OUT std_logic
		);
end TOP;

architecture Behavioral of TOP is
		

COMPONENT system
	PORT(
		fpga_0_RS232_RX_pin : IN std_logic;
		fpga_0_DIP_Switches_4Bit_GPIO_IO_I_pin : IN std_logic_vector(0 to 3);
		fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0_pin : IN std_logic;
		fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin : IN std_logic_vector(7 downto 0);
		fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0_pin : IN std_logic;
		fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0_pin : IN std_logic;
		fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin : IN std_logic;
		fpga_0_clk_1_sys_clk_pin : IN std_logic;
		fpga_0_rst_1_sys_rst_pin : IN std_logic;    
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQ_pin : INOUT std_logic_vector(31 downto 0);
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQS_pin : INOUT std_logic_vector(3 downto 0);
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQS_N_pin : INOUT std_logic_vector(3 downto 0);
		fpga_0_Hard_Ethernet_MAC_MDIO_0_pin : INOUT std_logic;      
		fpga_0_RS232_TX_pin : OUT std_logic;
		fpga_0_LEDs_8Bit_GPIO_IO_O_pin : OUT std_logic_vector(0 to 7);
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_A_pin : OUT std_logic_vector(12 downto 0);
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_BA_pin : OUT std_logic_vector(1 downto 0);
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_RAS_N_pin : OUT std_logic;
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_CAS_N_pin : OUT std_logic;
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_WE_N_pin : OUT std_logic;
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_CS_N_pin : OUT std_logic;
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_ODT_pin : OUT std_logic;
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_CKE_pin : OUT std_logic;
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_DM_pin : OUT std_logic_vector(3 downto 0);
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_CK_pin : OUT std_logic_vector(1 downto 0);
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_CK_N_pin : OUT std_logic_vector(1 downto 0);
		fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin : OUT std_logic;
		fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin : OUT std_logic_vector(7 downto 0);
		fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0_pin : OUT std_logic;
		fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0_pin : OUT std_logic;
		fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0_pin : OUT std_logic;
		fpga_0_Hard_Ethernet_MAC_MDC_0_pin : OUT std_logic;
		fpga_0_Hard_Ethernet_MAC_PHY_MII_INT_pin : OUT std_logic;
		
		xps_bram_if_cntlr_1_bram_BRAM_Rst_B_pin : IN std_logic;
		xps_bram_if_cntlr_1_bram_BRAM_Clk_B_pin : IN std_logic;
		xps_bram_if_cntlr_1_bram_BRAM_EN_B_pin : IN std_logic;
		xps_bram_if_cntlr_1_bram_BRAM_WEN_B_pin : IN std_logic_vector(0 to 3);
		xps_bram_if_cntlr_1_bram_BRAM_Addr_B_pin : IN std_logic_vector(0 to 31);
		xps_bram_if_cntlr_1_bram_BRAM_Dout_B_pin : IN std_logic_vector(0 to 31);
		xps_bram_if_cntlr_1_bram_BRAM_Din_B_pin : OUT std_logic_vector(0 to 31);
		
		test_GPIO_IO_O_pin : OUT std_logic_vector(0 to 31)
		);
	END COMPONENT;

attribute box_type : string;
attribute box_type of system : component is "user_black_box";

Signal xps_bram_if_cntlr_1_bram_BRAM_Rst_B_pin_s :  std_logic;
Signal xps_bram_if_cntlr_1_bram_BRAM_Clk_B_pin_s :  std_logic;
Signal xps_bram_if_cntlr_1_bram_BRAM_EN_B_pin_s :  std_logic;
Signal xps_bram_if_cntlr_1_bram_BRAM_WEN_B_pin_s :  std_logic_vector(0 to 3);
Signal xps_bram_if_cntlr_1_bram_BRAM_Addr_B_pin_s :  std_logic_vector(0 to 31);
Signal xps_bram_if_cntlr_1_bram_BRAM_Dout_B_pin_s :  std_logic_vector(0 to 31);
Signal xps_bram_if_cntlr_1_bram_BRAM_Din_B_pin_s :  std_logic_vector(0 to 31);
Signal stateMachine :  std_logic_vector(0 to 3);
Signal count :  std_logic_vector(0 to 3);
constant countnumber : integer := 4;

Signal test_GPIO_IO_O_pin_s :  std_logic_vector(0 to 31); 

attribute keep : string;
attribute keep of xps_bram_if_cntlr_1_bram_BRAM_Dout_B_pin_s : signal is "true";
attribute keep of xps_bram_if_cntlr_1_bram_BRAM_Addr_B_pin_s : signal is "true";

attribute keep of test_GPIO_IO_O_pin_s : signal is "true";

begin

	Inst_system: system PORT MAP(
		fpga_0_RS232_RX_pin => fpga_0_RS232_RX_pin,
		fpga_0_RS232_TX_pin => fpga_0_RS232_TX_pin,
		fpga_0_LEDs_8Bit_GPIO_IO_O_pin => fpga_0_LEDs_8Bit_GPIO_IO_O_pin,
		fpga_0_DIP_Switches_4Bit_GPIO_IO_I_pin => fpga_0_DIP_Switches_4Bit_GPIO_IO_I_pin,
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQ_pin => fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQ_pin,
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQS_pin => fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQS_pin,
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQS_N_pin => fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQS_N_pin,
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_A_pin => fpga_0_DDR2_SDRAM_16Mx32_DDR2_A_pin,
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_BA_pin => fpga_0_DDR2_SDRAM_16Mx32_DDR2_BA_pin,
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_RAS_N_pin => fpga_0_DDR2_SDRAM_16Mx32_DDR2_RAS_N_pin,
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_CAS_N_pin => fpga_0_DDR2_SDRAM_16Mx32_DDR2_CAS_N_pin,
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_WE_N_pin => fpga_0_DDR2_SDRAM_16Mx32_DDR2_WE_N_pin,
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_CS_N_pin => fpga_0_DDR2_SDRAM_16Mx32_DDR2_CS_N_pin,
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_ODT_pin => fpga_0_DDR2_SDRAM_16Mx32_DDR2_ODT_pin,
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_CKE_pin => fpga_0_DDR2_SDRAM_16Mx32_DDR2_CKE_pin,
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_DM_pin => fpga_0_DDR2_SDRAM_16Mx32_DDR2_DM_pin,
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_CK_pin => fpga_0_DDR2_SDRAM_16Mx32_DDR2_CK_pin,
		fpga_0_DDR2_SDRAM_16Mx32_DDR2_CK_N_pin => fpga_0_DDR2_SDRAM_16Mx32_DDR2_CK_N_pin,
		fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin => fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin,
		fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0_pin => fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0_pin,
		fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin => fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin,
		fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0_pin => fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0_pin,
		fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0_pin => fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0_pin,
		fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0_pin => fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0_pin,
		fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin => fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin,
		fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0_pin => fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0_pin,
		fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0_pin => fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0_pin,
		fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin => fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin,
		fpga_0_Hard_Ethernet_MAC_MDC_0_pin => fpga_0_Hard_Ethernet_MAC_MDC_0_pin,
		fpga_0_Hard_Ethernet_MAC_MDIO_0_pin => fpga_0_Hard_Ethernet_MAC_MDIO_0_pin,
		fpga_0_Hard_Ethernet_MAC_PHY_MII_INT_pin => fpga_0_Hard_Ethernet_MAC_PHY_MII_INT_pin,
		fpga_0_clk_1_sys_clk_pin => fpga_0_clk_1_sys_clk_pin,
		fpga_0_rst_1_sys_rst_pin => fpga_0_rst_1_sys_rst_pin,
		xps_bram_if_cntlr_1_bram_BRAM_Rst_B_pin => xps_bram_if_cntlr_1_bram_BRAM_Rst_B_pin_s,
		xps_bram_if_cntlr_1_bram_BRAM_Clk_B_pin => xps_bram_if_cntlr_1_bram_BRAM_Clk_B_pin_s,
		xps_bram_if_cntlr_1_bram_BRAM_EN_B_pin => xps_bram_if_cntlr_1_bram_BRAM_EN_B_pin_s,
		xps_bram_if_cntlr_1_bram_BRAM_WEN_B_pin => xps_bram_if_cntlr_1_bram_BRAM_WEN_B_pin_s,
		xps_bram_if_cntlr_1_bram_BRAM_Addr_B_pin => xps_bram_if_cntlr_1_bram_BRAM_Addr_B_pin_s,
		xps_bram_if_cntlr_1_bram_BRAM_Dout_B_pin => xps_bram_if_cntlr_1_bram_BRAM_Din_B_pin_s,
		xps_bram_if_cntlr_1_bram_BRAM_Din_B_pin => xps_bram_if_cntlr_1_bram_BRAM_Dout_B_pin_s,
		test_GPIO_IO_O_pin => test_GPIO_IO_O_pin_s
		-- xps_gpio_0_GPIO_IO_I_pin => xps_gpio_0_GPIO_IO_I_pin_s
	);

	
-- process (fpga_0_clk_1_sys_clk_pin, fpga_0_rst_1_sys_rst_pin)	
-- begin
	-- if (fpga_0_rst_1_sys_rst_pin = '1') then
		-- xps_bram_if_cntlr_1_bram_BRAM_Rst_B_pin_s <= '1';
		-- xps_bram_if_cntlr_1_bram_BRAM_WEN_B_pin_s <= "0000";
		-- xps_bram_if_cntlr_1_bram_BRAM_Addr_B_pin_s <= x"00000000";
		-- xps_bram_if_cntlr_1_bram_BRAM_Din_B_pin_s <= x"00000000";
		-- stateMachine <= "0000";
		-- count <= "0000";
	
	-- elsif (fpga_0_clk_1_sys_clk_pin'event and fpga_0_clk_1_sys_clk_pin = '1') then
		-- xps_bram_if_cntlr_1_bram_BRAM_Rst_B_pin_s <= '0';
		-- case stateMachine is
		
			-- when "0000" => xps_bram_if_cntlr_1_bram_BRAM_WEN_B_pin_s <= "1111";
						   -- xps_bram_if_cntlr_1_bram_BRAM_Addr_B_pin_s <= x"00000000";
						   -- xps_bram_if_cntlr_1_bram_BRAM_Din_B_pin_s <= x"CAFEDEAD";
						   -- if (count = countnumber) then
								-- stateMachine <= "0001";
								-- count <= "0000";
								-- xps_bram_if_cntlr_1_bram_BRAM_WEN_B_pin_s <= "0000";
							-- else
								-- count <= count + 1;
							-- end if;
					
			-- when "0001" => xps_bram_if_cntlr_1_bram_BRAM_WEN_B_pin_s <= "1111";
						   -- xps_bram_if_cntlr_1_bram_BRAM_Addr_B_pin_s <= x"00000001";
						   -- xps_bram_if_cntlr_1_bram_BRAM_Din_B_pin_s <= x"BEEFBEEF";		
						   -- if (count = countnumber) then
								-- stateMachine <= "0010";
								-- count <= "0000";
								-- xps_bram_if_cntlr_1_bram_BRAM_WEN_B_pin_s <= "0000";
							-- else
								-- count <= count + 1;
							-- end if;
					
			-- when "0010" => xps_bram_if_cntlr_1_bram_BRAM_WEN_B_pin_s <= "1111";
						   -- xps_bram_if_cntlr_1_bram_BRAM_Addr_B_pin_s <= x"00000002";
						   -- xps_bram_if_cntlr_1_bram_BRAM_Din_B_pin_s <= x"DEADBEEF";		
						   -- if (count = countnumber) then
								-- stateMachine <= "0011";
								-- count <= "0000";
								-- xps_bram_if_cntlr_1_bram_BRAM_WEN_B_pin_s <= "0000";
							-- else
								-- count <= count + 1;
							-- end if;
			
			-- when "0011" => xps_bram_if_cntlr_1_bram_BRAM_WEN_B_pin_s <= "1111";
						   -- xps_bram_if_cntlr_1_bram_BRAM_Addr_B_pin_s <= x"00000003";
						   -- xps_bram_if_cntlr_1_bram_BRAM_Din_B_pin_s <= x"AAAAAAAA";		
						   -- if (count = countnumber) then
								-- stateMachine <= "0100";
								-- count <= "0000";
								-- xps_bram_if_cntlr_1_bram_BRAM_WEN_B_pin_s <= "0000";
							-- else
								-- count <= count + 1;
							-- end if;		

			-- when "0100" => xps_bram_if_cntlr_1_bram_BRAM_WEN_B_pin_s <= "1111";
						   -- xps_bram_if_cntlr_1_bram_BRAM_Addr_B_pin_s <= x"00000004";
						   -- xps_bram_if_cntlr_1_bram_BRAM_Din_B_pin_s <= x"CBCBCBCB";		
						   -- if (count = countnumber) then
								-- stateMachine <= "0101";
								-- count <= "0000";
								-- xps_bram_if_cntlr_1_bram_BRAM_WEN_B_pin_s <= "0000";
							-- else
								-- count <= count + 1;
							-- end if;	
							
			-- when "0101" => xps_bram_if_cntlr_1_bram_BRAM_WEN_B_pin_s <= "1111";
						   -- xps_bram_if_cntlr_1_bram_BRAM_Addr_B_pin_s <= x"00000005";
						   -- xps_bram_if_cntlr_1_bram_BRAM_Din_B_pin_s <= x"FEEFBAAB";		
						   -- if (count = countnumber) then
								-- stateMachine <= "0000";
								-- count <= "0000";
								-- xps_bram_if_cntlr_1_bram_BRAM_WEN_B_pin_s <= "0000";
							-- else
								-- count <= count + 1;
							-- end if;	
							
			-- when others =>
			-- end case;
	
	-- end if;
-- end process;



process (fpga_0_clk_1_sys_clk_pin, fpga_0_rst_1_sys_rst_pin)	
begin
	if (fpga_0_rst_1_sys_rst_pin = '1') then
		xps_bram_if_cntlr_1_bram_BRAM_Rst_B_pin_s <= '1';
		xps_bram_if_cntlr_1_bram_BRAM_WEN_B_pin_s <= "0000";
		xps_bram_if_cntlr_1_bram_BRAM_Addr_B_pin_s <= x"00000000";
		xps_bram_if_cntlr_1_bram_BRAM_Din_B_pin_s <= x"00000000";
		stateMachine <= "0000";
		count <= "0000";

	
	elsif (fpga_0_clk_1_sys_clk_pin'event and fpga_0_clk_1_sys_clk_pin = '1') then
		xps_bram_if_cntlr_1_bram_BRAM_Rst_B_pin_s <= '0';
		case stateMachine is
		
			when "0000" => xps_bram_if_cntlr_1_bram_BRAM_WEN_B_pin_s <= "0000";
						   xps_bram_if_cntlr_1_bram_BRAM_Addr_B_pin_s <= x"00000000";
						   xps_bram_if_cntlr_1_bram_BRAM_Din_B_pin_s <= x"00000001";
						   if (count = countnumber) then
								stateMachine <= "0001";
								count <= "0000";
							else
								count <= count + 1;
							end if;
						   
			when "0001" => xps_bram_if_cntlr_1_bram_BRAM_WEN_B_pin_s <= "0000";
						   xps_bram_if_cntlr_1_bram_BRAM_Addr_B_pin_s <= x"00000001";
						   xps_bram_if_cntlr_1_bram_BRAM_Din_B_pin_s <= x"00000001";		
						   if (count = countnumber) then
								stateMachine <= "0010";
								count <= "0000";
							else
								count <= count + 1;
							end if;
					
			when "0010" => xps_bram_if_cntlr_1_bram_BRAM_WEN_B_pin_s <= "0000";
						   xps_bram_if_cntlr_1_bram_BRAM_Addr_B_pin_s <= x"00000002";
						   xps_bram_if_cntlr_1_bram_BRAM_Din_B_pin_s <= x"00000001";		
						   if (count = countnumber) then
								stateMachine <= "0011";
								count <= "0000";
							else
								count <= count + 1;
							end if;
						   
			when "0011" => xps_bram_if_cntlr_1_bram_BRAM_WEN_B_pin_s <= "0000";
						   xps_bram_if_cntlr_1_bram_BRAM_Addr_B_pin_s <= x"00000003";
						   xps_bram_if_cntlr_1_bram_BRAM_Din_B_pin_s <= x"00000001";		
						   if (count = countnumber) then
								stateMachine <= "0100";
								count <= "0000";
							else
								count <= count + 1;
							end if;		
							
			when "0100" => xps_bram_if_cntlr_1_bram_BRAM_WEN_B_pin_s <= "0000";
						   xps_bram_if_cntlr_1_bram_BRAM_Addr_B_pin_s <= x"FFFFC000";
						   xps_bram_if_cntlr_1_bram_BRAM_Din_B_pin_s <= x"00000001";		
						   if (count = countnumber) then
								stateMachine <= "0101";
								count <= "0000";
							else
								count <= count + 1;
							end if;	
			
			when "0101" => xps_bram_if_cntlr_1_bram_BRAM_WEN_B_pin_s <= "0000";
						   xps_bram_if_cntlr_1_bram_BRAM_Addr_B_pin_s <= x"FFFFC001";
						   xps_bram_if_cntlr_1_bram_BRAM_Din_B_pin_s <= x"00000001";		
						   if (count = countnumber) then
								stateMachine <= "0000";
								count <= "0000";
							else
								count <= count + 1;
							end if;

			when others =>
			end case;
	
	end if;
end process;

xps_bram_if_cntlr_1_bram_BRAM_Clk_B_pin_s <= fpga_0_clk_1_sys_clk_pin;
xps_bram_if_cntlr_1_bram_BRAM_EN_B_pin_s <= '1';
	
end Behavioral;





IN XPS

# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 11.1 Build EDK_L.29
# Tue May 05 09:00:44 2009
# Target Board:  Avnet Virtex-5 FX30T Mini Module Plus CX4 Rev 1.0
# Family:    virtex5
# Device:    XC5VFX30T
# Package:   FF665
# Speed Grade:  -2
# Processor number: 1
# Processor 1: ppc440_0
# Processor clock frequency: 400.0
# Bus clock frequency: 400.0
# Debug Interface: FPGA JTAG
# ##############################################################################
 PARAMETER VERSION = 2.1.0


 PORT fpga_0_RS232_RX_pin = fpga_0_RS232_RX_pin, DIR = I
 PORT fpga_0_RS232_TX_pin = fpga_0_RS232_TX_pin, DIR = O
 PORT fpga_0_LEDs_8Bit_GPIO_IO_O_pin = fpga_0_LEDs_8Bit_GPIO_IO_O_pin, DIR = O, VEC = [0:7]
 PORT fpga_0_DIP_Switches_4Bit_GPIO_IO_I_pin = fpga_0_DIP_Switches_4Bit_GPIO_IO_I_pin, DIR = I, VEC = [0:3]
 PORT fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQ_pin = fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQ_pin, DIR = IO, VEC = [31:0]
 PORT fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQS_pin = fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQS_pin, DIR = IO, VEC = [3:0]
 PORT fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQS_N_pin = fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQS_N_pin, DIR = IO, VEC = [3:0]
 PORT fpga_0_DDR2_SDRAM_16Mx32_DDR2_A_pin = fpga_0_DDR2_SDRAM_16Mx32_DDR2_A_pin, DIR = O, VEC = [12:0]
 PORT fpga_0_DDR2_SDRAM_16Mx32_DDR2_BA_pin = fpga_0_DDR2_SDRAM_16Mx32_DDR2_BA_pin, DIR = O, VEC = [1:0]
 PORT fpga_0_DDR2_SDRAM_16Mx32_DDR2_RAS_N_pin = fpga_0_DDR2_SDRAM_16Mx32_DDR2_RAS_N_pin, DIR = O
 PORT fpga_0_DDR2_SDRAM_16Mx32_DDR2_CAS_N_pin = fpga_0_DDR2_SDRAM_16Mx32_DDR2_CAS_N_pin, DIR = O
 PORT fpga_0_DDR2_SDRAM_16Mx32_DDR2_WE_N_pin = fpga_0_DDR2_SDRAM_16Mx32_DDR2_WE_N_pin, DIR = O
 PORT fpga_0_DDR2_SDRAM_16Mx32_DDR2_CS_N_pin = fpga_0_DDR2_SDRAM_16Mx32_DDR2_CS_N_pin, DIR = O
 PORT fpga_0_DDR2_SDRAM_16Mx32_DDR2_ODT_pin = fpga_0_DDR2_SDRAM_16Mx32_DDR2_ODT_pin, DIR = O
 PORT fpga_0_DDR2_SDRAM_16Mx32_DDR2_CKE_pin = fpga_0_DDR2_SDRAM_16Mx32_DDR2_CKE_pin, DIR = O
 PORT fpga_0_DDR2_SDRAM_16Mx32_DDR2_DM_pin = fpga_0_DDR2_SDRAM_16Mx32_DDR2_DM_pin, DIR = O, VEC = [3:0]
 PORT fpga_0_DDR2_SDRAM_16Mx32_DDR2_CK_pin = fpga_0_DDR2_SDRAM_16Mx32_DDR2_CK_pin, DIR = O, VEC = [1:0]
 PORT fpga_0_DDR2_SDRAM_16Mx32_DDR2_CK_N_pin = fpga_0_DDR2_SDRAM_16Mx32_DDR2_CK_N_pin, DIR = O, VEC = [1:0]
 PORT fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin = fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin, DIR = O
 PORT fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0_pin = fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0_pin, DIR = I
 PORT fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin = fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin, DIR = O, VEC = [7:0]
 PORT fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0_pin = fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0_pin, DIR = O
 PORT fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0_pin = fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0_pin, DIR = O
 PORT fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0_pin = fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0_pin, DIR = O
 PORT fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin = fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin, DIR = I, VEC = [7:0]
 PORT fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0_pin = fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0_pin, DIR = I
 PORT fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0_pin = fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0_pin, DIR = I
 PORT fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin = fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin, DIR = I
 PORT fpga_0_Hard_Ethernet_MAC_MDC_0_pin = fpga_0_Hard_Ethernet_MAC_MDC_0_pin, DIR = O
 PORT fpga_0_Hard_Ethernet_MAC_MDIO_0_pin = fpga_0_Hard_Ethernet_MAC_MDIO_0_pin, DIR = IO
 PORT fpga_0_Hard_Ethernet_MAC_PHY_MII_INT_pin = net_vcc, DIR = O
 PORT fpga_0_clk_1_sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
 PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1
 PORT xps_bram_if_cntlr_1_bram_BRAM_Rst_B_pin = xps_bram_if_cntlr_1_bram_BRAM_Rst_B, DIR = I
 PORT xps_bram_if_cntlr_1_bram_BRAM_Clk_B_pin = xps_bram_if_cntlr_1_bram_BRAM_Clk_B, DIR = I, SIGIS = CLK
 PORT xps_bram_if_cntlr_1_bram_BRAM_EN_B_pin = xps_bram_if_cntlr_1_bram_BRAM_EN_B, DIR = I
 PORT xps_bram_if_cntlr_1_bram_BRAM_WEN_B_pin = xps_bram_if_cntlr_1_bram_BRAM_WEN_B, DIR = I, VEC = [0:3]
 PORT xps_bram_if_cntlr_1_bram_BRAM_Addr_B_pin = xps_bram_if_cntlr_1_bram_BRAM_Addr_B, DIR = I, VEC = [0:31]
 PORT xps_bram_if_cntlr_1_bram_BRAM_Din_B_pin = xps_bram_if_cntlr_1_bram_BRAM_Din_B, DIR = O, VEC = [0:31]
 PORT xps_bram_if_cntlr_1_bram_BRAM_Dout_B_pin = xps_bram_if_cntlr_1_bram_BRAM_Dout_B, DIR = I, VEC = [0:31]
 PORT test_GPIO_IO_O_pin = test_GPIO_IO_O_pin, DIR = O, VEC = [0:31]


BEGIN ppc440_virtex5
 PARAMETER INSTANCE = ppc440_0
 PARAMETER C_IDCR_BASEADDR = 0b0000000000
 PARAMETER C_IDCR_HIGHADDR = 0b0011111111
 PARAMETER C_PPC440MC_ROW_CONFLICT_MASK = 0x000FFF80
 PARAMETER C_PPC440MC_BANK_CONFLICT_MASK = 0x00300000
 PARAMETER C_PPC440MC_CONTROL = 0xf850008f
 PARAMETER C_SPLB0_NUM_MPLB_ADDR_RNG = 0
 PARAMETER C_SPLB1_NUM_MPLB_ADDR_RNG = 0
 PARAMETER C_NUM_DMA = 1
 PARAMETER HW_VER = 1.01.a
 BUS_INTERFACE MPLB = plb_v46_0
 BUS_INTERFACE PPC440MC = ppc440_0_PPC440MC
 BUS_INTERFACE JTAGPPC = ppc440_0_jtagppc_bus
 BUS_INTERFACE RESETPPC = ppc_reset_bus
 BUS_INTERFACE LLDMA0 = Hard_Ethernet_MAC_LLINK0
 PORT CPMC440CLK = clk_400_0000MHzPLL0
 PORT CPMINTERCONNECTCLK = clk_200_0000MHzPLL0
 PORT CPMINTERCONNECTCLKNTO1 = net_vcc
 PORT EICC440EXTIRQ = ppc440_0_EICC440EXTIRQ
 PORT CPMMCCLK = clk_200_0000MHzPLL0_ADJUST
 PORT CPMPPCMPLBCLK = clk_100_0000MHzPLL0_ADJUST
 PORT CPMDMA0LLCLK = clk_100_0000MHzPLL0_ADJUST
 PORT DMA0TXIRQ = ppc440_0_DMA0TXIRQ
 PORT DMA0RXIRQ = ppc440_0_DMA0RXIRQ
 PORT CPMPPCS0PLBCLK = clk_100_0000MHzPLL0_ADJUST
END

BEGIN plb_v46
 PARAMETER INSTANCE = plb_v46_0
 PARAMETER C_DCR_INTFCE = 0
 PARAMETER C_FAMILY = virtex5
 PARAMETER HW_VER = 1.04.a
 PORT PLB_Clk = clk_100_0000MHzPLL0_ADJUST
 PORT SYS_Rst = sys_bus_reset
END

BEGIN xps_bram_if_cntlr
 PARAMETER INSTANCE = xps_bram_if_cntlr_1
 PARAMETER C_SPLB_NATIVE_DWIDTH = 32
 PARAMETER C_SPLB_SUPPORT_BURSTS = 1
 PARAMETER C_SPLB_P2P = 0
 PARAMETER C_FAMILY = virtex5
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_SPLB_SMALLEST_MASTER = 128
 PARAMETER C_BASEADDR = 0xffffc000
 PARAMETER C_HIGHADDR = 0xffffffff
 BUS_INTERFACE SPLB = plb_v46_0
 BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
END

BEGIN bram_block
 PARAMETER INSTANCE = xps_bram_if_cntlr_1_bram
 PARAMETER C_FAMILY = virtex5
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
 PORT BRAM_Rst_B = xps_bram_if_cntlr_1_bram_BRAM_Rst_B
 PORT BRAM_Clk_B = xps_bram_if_cntlr_1_bram_BRAM_Clk_B
 PORT BRAM_EN_B = xps_bram_if_cntlr_1_bram_BRAM_EN_B
 PORT BRAM_WEN_B = xps_bram_if_cntlr_1_bram_BRAM_WEN_B
 PORT BRAM_Addr_B = xps_bram_if_cntlr_1_bram_BRAM_Addr_B
 PORT BRAM_Din_B = xps_bram_if_cntlr_1_bram_BRAM_Din_B
 PORT BRAM_Dout_B = xps_bram_if_cntlr_1_bram_BRAM_Dout_B
END

BEGIN xps_uartlite
 PARAMETER INSTANCE = RS232
 PARAMETER C_FAMILY = virtex5
 PARAMETER C_BAUDRATE = 19200
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_ODD_PARITY = 0
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_BASEADDR = 0x84000000
 PARAMETER C_HIGHADDR = 0x8400ffff
 BUS_INTERFACE SPLB = plb_v46_0
 PORT RX = fpga_0_RS232_RX_pin
 PORT TX = fpga_0_RS232_TX_pin
 PORT Interrupt = RS232_Interrupt
END

BEGIN xps_gpio
 PARAMETER INSTANCE = LEDs_8Bit
 PARAMETER C_FAMILY = virtex5
 PARAMETER C_ALL_INPUTS = 0
 PARAMETER C_GPIO_WIDTH = 8
 PARAMETER C_INTERRUPT_PRESENT = 0
 PARAMETER C_IS_DUAL = 0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0x81400000
 PARAMETER C_HIGHADDR = 0x8140ffff
 BUS_INTERFACE SPLB = plb_v46_0
 PORT GPIO_IO_O = fpga_0_LEDs_8Bit_GPIO_IO_O_pin
END

BEGIN xps_gpio
 PARAMETER INSTANCE = DIP_Switches_4Bit
 PARAMETER C_FAMILY = virtex5
 PARAMETER C_ALL_INPUTS = 1
 PARAMETER C_GPIO_WIDTH = 4
 PARAMETER C_INTERRUPT_PRESENT = 0
 PARAMETER C_IS_DUAL = 0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0x81420000
 PARAMETER C_HIGHADDR = 0x8142ffff
 BUS_INTERFACE SPLB = plb_v46_0
 PORT GPIO_IO_I = fpga_0_DIP_Switches_4Bit_GPIO_IO_I_pin
END

BEGIN ppc440mc_ddr2
 PARAMETER INSTANCE = DDR2_SDRAM_16Mx32
 PARAMETER C_DDR_BAWIDTH = 2
 PARAMETER C_NUM_CLK_PAIRS = 2
 PARAMETER C_DDR_DWIDTH = 32
 PARAMETER C_DDR_CAWIDTH = 9
 PARAMETER C_NUM_RANKS_MEM = 1
 PARAMETER C_CS_BITS = 0
 PARAMETER C_DDR_DM_WIDTH = 4
 PARAMETER C_DQ_BITS = 5
 PARAMETER C_DDR2_ODT_WIDTH = 1
 PARAMETER C_DDR2_ADDT_LAT = 1
 PARAMETER C_INCLUDE_ECC_SUPPORT = 0
 PARAMETER C_DQS_BITS = 2
 PARAMETER C_DDR_DQS_WIDTH = 4
 PARAMETER C_DDR_RAWIDTH = 13
 PARAMETER C_DDR_BURST_LENGTH = 4
 PARAMETER C_DDR_CAS_LAT = 3
 PARAMETER C_REG_DIMM = 0
 PARAMETER C_MIB_MC_CLOCK_RATIO = 1
 PARAMETER C_DDR_TREFI = 7800
 PARAMETER C_DDR_TRAS = 40000
 PARAMETER C_DDR_TRCD = 15000
 PARAMETER C_DDR_TRFC = 70000
 PARAMETER C_DDR_TRP = 15000
 PARAMETER C_DDR_TRTP = 7500
 PARAMETER C_DDR_TWR = 15000
 PARAMETER C_DDR_TWTR = 10000
 PARAMETER C_MC_MIBCLK_PERIOD_PS = 5000
 PARAMETER C_IDEL_HIGH_PERF = TRUE
 PARAMETER C_NUM_IDELAYCTRL = 2
 PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y3-IDELAYCTRL_X0Y4
 PARAMETER C_DQS_IO_COL = 0b00000000
 PARAMETER C_DQ_IO_MS = 0b10101010110101010101101010101010
 PARAMETER HW_VER = 2.00.b
 PARAMETER C_MEM_BASEADDR = 0x00000000
 PARAMETER C_MEM_HIGHADDR = 0x03ffffff
 BUS_INTERFACE PPC440MC = ppc440_0_PPC440MC
 PORT mc_mibclk = clk_200_0000MHzPLL0_ADJUST
 PORT mi_mcclk90 = clk_200_0000MHz90PLL0_ADJUST
 PORT mi_mcreset = sys_bus_reset
 PORT mi_mcclkdiv2 = clk_100_0000MHzPLL0_ADJUST
 PORT mi_mcclk_200 = clk_200_0000MHzPLL0
 PORT DDR2_DQ = fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQ_pin
 PORT DDR2_DQS = fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQS_pin
 PORT DDR2_DQS_N = fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQS_N_pin
 PORT DDR2_A = fpga_0_DDR2_SDRAM_16Mx32_DDR2_A_pin
 PORT DDR2_BA = fpga_0_DDR2_SDRAM_16Mx32_DDR2_BA_pin
 PORT DDR2_RAS_N = fpga_0_DDR2_SDRAM_16Mx32_DDR2_RAS_N_pin
 PORT DDR2_CAS_N = fpga_0_DDR2_SDRAM_16Mx32_DDR2_CAS_N_pin
 PORT DDR2_WE_N = fpga_0_DDR2_SDRAM_16Mx32_DDR2_WE_N_pin
 PORT DDR2_CS_N = fpga_0_DDR2_SDRAM_16Mx32_DDR2_CS_N_pin
 PORT DDR2_ODT = fpga_0_DDR2_SDRAM_16Mx32_DDR2_ODT_pin
 PORT DDR2_CKE = fpga_0_DDR2_SDRAM_16Mx32_DDR2_CKE_pin
 PORT DDR2_DM = fpga_0_DDR2_SDRAM_16Mx32_DDR2_DM_pin
 PORT DDR2_CK = fpga_0_DDR2_SDRAM_16Mx32_DDR2_CK_pin
 PORT DDR2_CK_N = fpga_0_DDR2_SDRAM_16Mx32_DDR2_CK_N_pin
END

BEGIN xps_ll_temac
 PARAMETER INSTANCE = Hard_Ethernet_MAC
 PARAMETER C_NUM_IDELAYCTRL = 2
 PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y5-IDELAYCTRL_X1Y5
 PARAMETER C_FAMILY = virtex5
 PARAMETER C_PHY_TYPE = 1
 PARAMETER C_TEMAC1_ENABLED = 0
 PARAMETER C_BUS2CORE_CLK_RATIO = 1
 PARAMETER C_TEMAC_TYPE = 0
 PARAMETER C_TEMAC0_PHYADDR = 0b00000000000000000000000000000001
 PARAMETER HW_VER = 2.03.a
 PARAMETER C_BASEADDR = 0x81c00000
 PARAMETER C_HIGHADDR = 0x81c7ffff
 BUS_INTERFACE SPLB = plb_v46_0
 BUS_INTERFACE LLINK0 = Hard_Ethernet_MAC_LLINK0
 PORT TemacIntc0_Irpt = Hard_Ethernet_MAC_TemacIntc0_Irpt
 PORT TemacPhy_RST_n = fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin
 PORT GTX_CLK_0 = clk_125_0000MHz
 PORT REFCLK = clk_200_0000MHzPLL0
 PORT LlinkTemac0_CLK = clk_100_0000MHzPLL0_ADJUST
 PORT MII_TX_CLK_0 = fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0_pin
 PORT GMII_TXD_0 = fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin
 PORT GMII_TX_EN_0 = fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0_pin
 PORT GMII_TX_ER_0 = fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0_pin
 PORT GMII_TX_CLK_0 = fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0_pin
 PORT GMII_RXD_0 = fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin
 PORT GMII_RX_DV_0 = fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0_pin
 PORT GMII_RX_ER_0 = fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0_pin
 PORT GMII_RX_CLK_0 = fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin
 PORT MDC_0 = fpga_0_Hard_Ethernet_MAC_MDC_0_pin
 PORT MDIO_0 = fpga_0_Hard_Ethernet_MAC_MDIO_0_pin
END

BEGIN edk_bufg
 PARAMETER INSTANCE = clkin_bufg
 PARAMETER HW_VER = 1.00.a
 PORT in_clk = dcm_clk_s
 PORT out_clk = dcm_clk_s_bufg
END

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER C_CLKIN_FREQ = 100000000
 PARAMETER C_CLKOUT0_FREQ = 100000000
 PARAMETER C_CLKOUT0_PHASE = 0
 PARAMETER C_CLKOUT0_GROUP = PLL0_ADJUST
 PARAMETER C_CLKOUT0_BUF = TRUE
 PARAMETER C_CLKOUT1_FREQ = 125000000
 PARAMETER C_CLKOUT1_PHASE = 0
 PARAMETER C_CLKOUT1_GROUP = NONE
 PARAMETER C_CLKOUT1_BUF = TRUE
 PARAMETER C_CLKOUT2_FREQ = 200000000
 PARAMETER C_CLKOUT2_PHASE = 90
 PARAMETER C_CLKOUT2_GROUP = PLL0_ADJUST
 PARAMETER C_CLKOUT2_BUF = TRUE
 PARAMETER C_CLKOUT3_FREQ = 200000000
 PARAMETER C_CLKOUT3_PHASE = 0
 PARAMETER C_CLKOUT3_GROUP = PLL0
 PARAMETER C_CLKOUT3_BUF = TRUE
 PARAMETER C_CLKOUT4_FREQ = 200000000
 PARAMETER C_CLKOUT4_PHASE = 0
 PARAMETER C_CLKOUT4_GROUP = PLL0_ADJUST
 PARAMETER C_CLKOUT4_BUF = TRUE
 PARAMETER C_CLKOUT5_FREQ = 400000000
 PARAMETER C_CLKOUT5_PHASE = 0
 PARAMETER C_CLKOUT5_GROUP = PLL0
 PARAMETER C_CLKOUT5_BUF = TRUE
 PARAMETER HW_VER = 3.02.a
 PORT CLKIN = dcm_clk_s_bufg
 PORT CLKOUT0 = clk_100_0000MHzPLL0_ADJUST
 PORT CLKOUT1 = clk_125_0000MHz
 PORT CLKOUT2 = clk_200_0000MHz90PLL0_ADJUST
 PORT CLKOUT3 = clk_200_0000MHzPLL0
 PORT CLKOUT4 = clk_200_0000MHzPLL0_ADJUST
 PORT CLKOUT5 = clk_400_0000MHzPLL0
 PORT RST = net_gnd
 PORT LOCKED = Dcm_all_locked
END

BEGIN jtagppc_cntlr
 PARAMETER INSTANCE = jtagppc_cntlr_inst
 PARAMETER HW_VER = 2.01.c
 BUS_INTERFACE JTAGPPC0 = ppc440_0_jtagppc_bus
END

BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER HW_VER = 2.00.a
 BUS_INTERFACE RESETPPC0 = ppc_reset_bus
 PORT Slowest_sync_clk = clk_100_0000MHzPLL0_ADJUST
 PORT Ext_Reset_In = sys_rst_s
 PORT Dcm_locked = Dcm_all_locked
 PORT Bus_Struct_Reset = sys_bus_reset
 PORT Peripheral_Reset = sys_periph_reset
END

BEGIN xps_intc
 PARAMETER INSTANCE = xps_intc_0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0x81800000
 PARAMETER C_HIGHADDR = 0x8180ffff
 BUS_INTERFACE SPLB = plb_v46_0
 PORT Intr = ppc440_0_DMA0TXIRQ & ppc440_0_DMA0RXIRQ & RS232_Interrupt & Hard_Ethernet_MAC_TemacIntc0_Irpt
 PORT Irq = ppc440_0_EICC440EXTIRQ
END

BEGIN xps_gpio
 PARAMETER INSTANCE = test
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_ALL_INPUTS = 1
 PARAMETER C_GPIO_WIDTH = 32
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_FAMILY = virtex5
 PARAMETER C_INTERRUPT_PRESENT = 0
 PARAMETER C_BASEADDR = 0x81440000
 PARAMETER C_HIGHADDR = 0x8144ffff
 BUS_INTERFACE SPLB = plb_v46_0
 PORT GPIO_IO_O = test_GPIO_IO_O_pin
END







IN SDK

/*
 * Copyright (c) 2009 Xilinx, Inc.  All rights reserved.
 *
 * Xilinx, Inc.
 * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
 * COURTESY TO YOU.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
 * ONE POSSIBLE   IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
 * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
 * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
 * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
 * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
 * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
 * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
 * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
 * AND FITNESS FOR A PARTICULAR PURPOSE.
 *
 */

#include <stdio.h>
#include <string.h>
#include "xparameters.h"
#include "xgpio.h"

#include "lwip/err.h"
#include "lwip/tcp.h"

int transfer_data() {
	return 0;
}

void print_app_header()
{
	xil_printf("\n\r\n\r-----lwIP TCP echo server ------\n\r");
	xil_printf("TCP packets sent to port 6001 will be echoed back\n\r");
}

err_t recv_callback(void *arg, struct tcp_pcb *tpcb,
                               struct pbuf *p, err_t err)
{
	/* do not read the packet if we are not in ESTABLISHED state */
#if 0
	if (tpcb->state >= 5 && tpcb->state <= 8) {
		tcp_close(tpcb);
		if (p)
			pbuf_free(p);
		//xil_printf("Connection (%d) closed\n\r", (int)(arg));
		return;
	} else if (tpcb->state > 8)
		return;
#else
	if (!p) {
		tcp_close(tpcb);
		tcp_recv(tpcb, NULL);
		return ERR_OK;
	}
#endif

	/* indicate that the packet has been received */
	tcp_recved(tpcb, p->len);

	/* echo back the payload */
	/* in this case, we assume that the payload is < TCP_SND_BUF */
	if (tcp_sndbuf(tpcb) > p->len) {
		err = tcp_write(tpcb, p->payload, p->len, 1);

		xil_printf("caracter send : %d\n\r",*((char*)p->payload));
		xil_printf("caracter send : %d\n\r",p->len);
		
		//*(volatile unsigned int*)(XPAR_XPS_BRAM_IF_CNTLR_1_BASEADDR) = 0xAAAA5555;
		//XGpio_mWriteReg(XPAR_XPS_BRAM_IF_CNTLR_1_BASEADDR, 0, 3);
		//XIo_Out32(XPAR_XPS_BRAM_IF_CNTLR_1_BASEADDR, 0xAAAA5555); 
		
		Xuint32 data;
		data = XIo_In32(XPAR_XPS_BRAM_IF_CNTLR_1_BASEADDR);
		xil_printf("\tread from BRAM : 0x%X\r\n",data);

		XIo_Out32(XPAR_XPS_BRAM_IF_CNTLR_1_BASEADDR,*((int*)p->payload));
		xil_printf("\twriting : 0x%X\r\n",*((int*)p->payload)); 
		
		
	} else
		print("no space in tcp_sndbuf\n\r");

	/* free the received pbuf */
	pbuf_free(p);

	return ERR_OK;
}

err_t accept_callback(void *arg, struct tcp_pcb *newpcb, err_t err)
{
	static int connection = 1;

	//xil_printf("Connection (%d) Accepted\n\r", connection);

	/* set the receive callback for this connection */
	tcp_recv(newpcb, recv_callback);

	/* just use an integer number indicating the connection id as the 
	   callback argument */
	tcp_arg(newpcb, (void*)connection);

	/* increment for subsequent accepted connections */
	connection++;

	return ERR_OK;
}


int start_application()
{
	struct tcp_pcb *pcb;
	err_t err;
	unsigned port = 7;

	/* create new TCP PCB structure */
	pcb = tcp_new();
	if (!pcb) {
		xil_printf("Error creating PCB. Out of Memory\n\r");
		return -1;
	}
	
	/* bind to specified @port */
	err = tcp_bind(pcb, IP_ADDR_ANY, port);
	if (err != ERR_OK) {
		xil_printf("Unable to bind to port %d: err = %d\n\r", port, err);
		return -2;
	}

	/* we do not need any arguments to callback functions */
	tcp_arg(pcb, NULL);

	/* listen for connections */
	pcb = tcp_listen(pcb);
	if (!pcb) {
		xil_printf("Out of memory while tcp_listen\n\r");
		return -3;
	}

	/* specify callback to use for incoming connections */
	tcp_accept(pcb, accept_callback);

	xil_printf("tcp echo server started @ port %d\n\r", port);

	return 0;
}

Open in new window

0
 

Author Comment

by:DBTechnique
Comment Utility
actually i found another way to do what i want, by using XGpio

i'm using this to write :
Xuint32 data;
XGpio_mWriteReg(XPAR_ComPPC_VHDL_BASEADDR, 0, *((int*)p->payload));

and that to read :            
data = XGpio_mReadReg(XPAR_ComVHDL_PPC_BASEADDR, 0);

it's working well, but now my problem is to send back data by the tcp/ip

now i'm writing a data by keyboard, this data is send by "XPAR_ComPPC_VHDL_BASEADDR" to my vhdl code that process the data and send back another data.
the process data is get by "XPAR_ComVHDL_PPC_BASEADDR".
until here everything is fine.

next step is to take this new data (32 bits) and send it back to the output (command prompt in windows).
i'm using :
err = tcp_write(tpcb, p->payload, p->len, 1); => to send back the same caractere that input prviously and it's work well
so i tried to use:
err = tcp_write(tpcb, (int*)data, sizeof(data), 1); => in order to send back my process data but it doesn't work

do you have an idea ? i think it's just my C code that is not good but i don't know how to write that
0
 
LVL 12

Accepted Solution

by:
HappyCactus earned 0 total points
Comment Utility
p->paylod is a char * ? so you must use

err = tcp_write(tcpb, (int *) &data, sizeof(data), 1);

(note the "&")
0
 

Author Comment

by:DBTechnique
Comment Utility
ok thank you !!
i think from now it should be ok....i hope :)

thanks for all your advices
0
 
LVL 12

Expert Comment

by:HappyCactus
Comment Utility
I didn't suggested you to use a dpram, but a flipflop or latch.
I do not want to object your closing decision, but...
0
 
LVL 12

Expert Comment

by:HappyCactus
Comment Utility
The selected solution is NOT a solution to the question.
The following comments answer (partially) to the question, and should be accepted:

http:#a33732912
http:#a33732897
http:#a33680156
(http:#a33646100)

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by:DBTechnique
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Hello,
Sorry it was a mistake. I wanted to close the topic since I got it working.
Please give the points to HappyCactus.
Regarding the correct solution, it is hard to tell which one should be considered. They all provide some pieces of information.
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by:HappyCactus
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0 points?
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by:DBTechnique
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Admin : Please advise me about how I can send the points to HappyCactus.
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