troubleshooting Question

Hey,

I had a quick question about IF statements in VHDL, for some reason I keep getting this error:

ERROR:HDLParsers:164 - "C:/Xilinx/Workspace/Homework3/homework3.vhd" Line 23. parse error, unexpected IF

I have tried everything I could think of, and looked a little through google, but I can't figure out why it doesn't like the IF statement.

Appreciate any help on this.

I had a quick question about IF statements in VHDL, for some reason I keep getting this error:

ERROR:HDLParsers:164 - "C:/Xilinx/Workspace/Homew

I have tried everything I could think of, and looked a little through google, but I can't figure out why it doesn't like the IF statement.

Appreciate any help on this.

```
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity homework3 is
Port ( num1 : in STD_LOGIC_VECTOR(1 downto 0);
num2 : in STD_LOGIC_VECTOR(1 downto 0);
result : out STD_LOGIC_VECTOR(3 downto 0));
end homework3;
architecture Behavioral of homework3 is
begin
--process (num1, num2)
--begin
if( (num1 = "00") or (num2 = "00") ) then
result <= "0000";
else if( (num1 = "01") and (num2 = "01") ) then
result <= "0001";
else if( (num1 = "01") and (num2 = "10") ) then
result <= "0010";
else if( (num1 = "10") and (num2 = "01") ) then
result <= "0010";
else if( (num1 = "01") and (num2 = "11") ) then
result <= "0011";
else if( (num1 = "11") and (num2 = "01") ) then
result <= "0011";
else if( (num1 = "10") and (num2 = "11") ) then
result <= "0110";
else if( (num1 = "11") and (num2 = "10") ) then
result <= "0110";
else if( (num1 = "10") and (num2 = "10") ) then
result <= "0100";
else
result <= "1001";
end if;
--end process;
end Behavioral;
```

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