A question about if statements in VHDL

Hey,

        I had a quick question about IF statements in VHDL, for some reason I keep getting this error:

ERROR:HDLParsers:164 - "C:/Xilinx/Workspace/Homework3/homework3.vhd" Line 23. parse error, unexpected IF

I have tried everything I could think of, and looked a little through google, but I can't figure out why it doesn't like the IF statement.

Appreciate any help on this.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity homework3 is
    Port ( num1 : in  STD_LOGIC_VECTOR(1 downto 0);
           num2 : in  STD_LOGIC_VECTOR(1 downto 0);
           result : out  STD_LOGIC_VECTOR(3 downto 0));
end homework3;

architecture Behavioral of homework3 is

begin
	--process (num1, num2)
	--begin
	if( (num1 = "00") or (num2 = "00") ) then
		result <= "0000";
	else if( (num1 = "01") and (num2 = "01") ) then
		result <= "0001";
	else if( (num1 = "01") and (num2 = "10") ) then
		result <= "0010";
	else if( (num1 = "10") and (num2 = "01") ) then
		result <= "0010";
	else if( (num1 = "01") and (num2 = "11") ) then
		result <= "0011";
	else if( (num1 = "11") and (num2 = "01") ) then
		result <= "0011";
	else if( (num1 = "10") and (num2 = "11") ) then
		result <= "0110";
	else if( (num1 = "11") and (num2 = "10") ) then
		result <= "0110";
	else if( (num1 = "10") and (num2 = "10") ) then
		result <= "0100";
	else
		result <= "1001";
	end if;
	--end process;

end Behavioral;

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errangAsked:
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KendorCommented:
everytime you open up an "if" you have to end it with "end if;"

so basically what you are looking for is "elsif"

if .... then
elsif ... then
else
end if;

that should work :)
(make sure you reenable the process  - you have uncommented it now)

a side note on better code:
try to have a look at the "case" statement when using the process or the "select ... when" statement if you want to do it without
for your case you could for example do the following:

process....
variable temp: std_logic_vector(3 downto 0);
...
begin
...

temp := num1 & num2; -- here you concatenate the two inputs you can then use them in case:

case temp is
  when "00--" | "--00" => result <= "0000"; --- this does not work with all fpgas or synthesis tools. if after the case...
  when "0101"      => result <= "0001";
  when "0110" | "1001" => result <= "0010";
  when "0111" | "1101" => result <= "0011";
  when "1011" | "1110" => result <= "0110";
  when "1010" => result <= "0100";
  when others => result <= "1001";
end case;


end process;



or the select when would the look like

with num1&num2 select
  result <= "0100" when "1010" ,
                   ...,
                 "1001 when others;
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errangAuthor Commented:
Ah, awesome.

Been programming java so long didn't occur to me as what was wrong with it.. lol.
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