A question about a dual-edge detector

Hey,

       I was just trying to make a dual-edge moore based detector, but for some reason its not working correctly... this is what I got so far with the help of some code from a book.

library ieee;
use ieee.std_logic_1164.all;

entity edge_detect is
   port(
          clk, reset:  in std_logic;
          level:  in std_logic;
          tick:   out std_logic;
   );
end edge_detect;

architecture moore_arch of edge_detect is
    type state_type is (zero, edge, one);
    signal state_reg, state_next:   state_type;

begin
     process(clk, reset)
     begin
         if (reset = '1') then
            state_reg <= zero;
         elsif (clk'event and clk = '1') then
            state_reg <= state_next;
         end if;
      end process;

      process(state_reg, level)
      begin
          state_next <= state_reg;
          tick <= '0';
          case state_reg is

          when zero =>
             if (level = '1') then
                state_next <= edge;
             end if;
           
          when one =>
             if (level = '0') then
                state_next <= edge;
             end if;
         
          when edge => tick <= '1';
            if (level = '1') then
               state_next <= one;
            else
               state_next <= zero;
            end if;
          end case;
       end process;
end moore_arch;

I'm not sure what the problem is... far as I understand all a dual-edge detector does is tick on both rising and falling edges, so with my logic, the program calls the edge case when the clock ticks a 1 or 0.  

Also, I'm not sure how to go about writing a test bench for this program, because I'm supposed to catch the output in a variable, right?

I'm a beginner in VHDL, so I'd appreciate any example programs/pointers.

Appreciate any help on this.