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GCC Makefile, how to generate lst or lss with c code embedded to lst.

Here the attached makefile where I have simple makefile template (part of learning with multiple h and c code)
=========================================================
# ------------- SOURCE FILE ------------------------
OBJECTS = main.o runme.o
#OBJECTS = main.c runme.c
#--------------TARGETS EXE -------------------------
TARGET = go
#--------------Folder Path--------------------------
vpath %.c src
vpath %.h include
vpath %.o obj
# ------------- COMPILER OPTIONS -------------------
CFLAGS=-ggdb -Wall -std=c99 -I include
CC=gcc

# ------------- TARGETS ----------------------------
all: $(TARGET)

$(TARGET): $(OBJECTS)
      $(CC) $(OBJECTS) $(CFLAGS) -o $(TARGET)

# ------------- CLEAN UP ----------------------------
.PHONY: clean
clean:
      rm -f *.o *.out
      
# -------------- DEPENDENCIES ---------------------
runme.o: runme.h
main.o: main.h runme.h
=======================================================

I need to embedded asm with code via lst or lss or s. I do not know how to add option to make it work as I tried several time

(a) what the difference between lst, lss and s
(b) What modification to provides txt files with asm with embedded c code
(c) I need to put .o code into object folder, how

Thanks

I'm using cygwin for training purpose and then work on UNIX (linix server). It use GNU toolchain.


0
Richard Payne
Asked:
Richard Payne
1 Solution
 
asurianuCommented:
a)  
LST is a dis assembly listing having source code in between. You may not get exact mapping if your compiler has higher optimization
LST assembly listing
.s - is plain assembly code file

b) to generate lst you need to add in your compiler flag rule
-adhlns=$(<:%.c=$(OBJDIR)/%.lst)

c) create a variable say OBJDIR having object directory location and your rule should looks like
$(TARGET): $(OBJECTS)
      $(CC) $(OBJECTS) $(CFLAGS) -o $(OBJDIR)/$(TARGET)


0
 
Richard PayneChief Technology EngineerAuthor Commented:
okay
0
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