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How to improve the LWIP speed

Posted on 2010-11-29
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Last Modified: 2012-05-10
Hi,

I'm using a FPGA Xilinx virtex5 with a PPC440 embedded (400Mhz with a general clk at 100Mhz).
In order to handle the TCP/IP communication with a computer, i'm using the LWIP 1.3.0 in RAW mode with standalone.

It seems to work well, but i have a problem of throughput. Actually if i send a lot of data without checking them i can reach a throughput near 250Mbits/s. That is really good, but under this condition i can see (with a sniffer like wireshark) there are a lot of data that didn't come out on the LAN. I don't know where they are lost.

If i decrease my throughput in order to have no data lost i can reach only 9Mbits/s that is too slow for my application. Actually for my application i need at least 40Mbits/s (5MBytes/s).

I'm beginner with LWIP, but i red there are a lot of optimization parameters as buffer size or whatever. Also i red about LWIP v3.0, is it better ? what should i do ?

Can someone help me to increase the speed of my LWIP please.

Thank you very much.
David
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Question by:DBTechnique
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Expert Comment

by:HappyCactus
Comment Utility
What kind of socket are you using for your application? TCP or UDP or RAW?
If you can't see the packets on the wire, it is probable that you have a problem at hardware levels. It could be that the ethernet controller is not able to sustain such an high transfert rate. But it could also be a software problem - maybe the DMA transfer isn't complete when you start a new transfer, or something similar.
It's difficult to suggest you a strategy to determine where the problem is without knowing the project details, but firstly I would check the hardware layer. See if the eth controller is running correctly, check carefully all the diagnostic signals and the hardware and all the status register on software, checking for overruns. After that, check the driver if working correctly, again, check all diagnostic codes and status codes you have.
Since the eth controller is a "soft" core, you could also change the controller.
Also, see if you can optimize the hardware, for example, running an higher clock, optimize the compilation or so on...
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Author Comment

by:DBTechnique
Comment Utility
Thanks for your answer, but since i am beginner it's a bit complex to follow all your advises.
First i can tell that I would like to use TCP socket.

Now to can give you more details i need to ask you some questions:
- when you say HW stuff are you speaking about the TEMAC or the phy?
- about DMA i didn't find out how to set it up, i red that it should be automatic setup, is it true ?
- how to check DMA ?
- when you say to check status registers, can you be more precise and tell me wich one cause i don't know about what you are speaking.
- how to check the driver ? where is the diver ?

I can give you all details you want if you ask me precisely what you need cause i don't know so much about these stuffs.

thank you



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LVL 12

Expert Comment

by:HappyCactus
Comment Utility
When I am talking about hardware, I am referring to the controller, not the ethernet transceiver that should work out-of-box.
I do not know which controller are you using, so I cannot give you any address about the registers or signals you should check, but generally speaking, any register that reports some error condition.
About DMA, again, I do not know hot you implemented your interfacing; maybe you are using no DMA, so implementing the DMA transfer instead of interrupt driving should help a lot; so check carefully if you can implement the DMA transfer.
with the term "driver", I mean to refer to your routines that drives the ethernet controller.
Hope that helps, sorry for not being more precise.
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Author Comment

by:DBTechnique
Comment Utility
Cause it's difficult for me to understand what information you need, i copy my .mhs and .mss
About DMA i don't know how to check or implement it. where can i see if i'm using it or no?
Thanks for your help

---- MHS ----
# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 11.1 Build EDK_L.29
# Tue May 05 09:00:44 2009
# Target Board:  Avnet Virtex-5 FX30T Mini Module Plus CX4 Rev 1.0
# Family:    virtex5
# Device:    XC5VFX30T
# Package:   FF665
# Speed Grade:  -2
# Processor number: 1
# Processor 1: ppc440_0
# Processor clock frequency: 400.0
# Bus clock frequency: 400.0
# Debug Interface: FPGA JTAG
# ##############################################################################
 PARAMETER VERSION = 2.1.0


 PORT fpga_0_RS232_RX_pin = fpga_0_RS232_RX_pin, DIR = I
 PORT fpga_0_RS232_TX_pin = fpga_0_RS232_TX_pin, DIR = O
 PORT fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQ_pin = fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQ_pin, DIR = IO, VEC = [31:0]
 PORT fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQS_pin = fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQS_pin, DIR = IO, VEC = [3:0]
 PORT fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQS_N_pin = fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQS_N_pin, DIR = IO, VEC = [3:0]
 PORT fpga_0_DDR2_SDRAM_16Mx32_DDR2_A_pin = fpga_0_DDR2_SDRAM_16Mx32_DDR2_A_pin, DIR = O, VEC = [12:0]
 PORT fpga_0_DDR2_SDRAM_16Mx32_DDR2_BA_pin = fpga_0_DDR2_SDRAM_16Mx32_DDR2_BA_pin, DIR = O, VEC = [1:0]
 PORT fpga_0_DDR2_SDRAM_16Mx32_DDR2_RAS_N_pin = fpga_0_DDR2_SDRAM_16Mx32_DDR2_RAS_N_pin, DIR = O
 PORT fpga_0_DDR2_SDRAM_16Mx32_DDR2_CAS_N_pin = fpga_0_DDR2_SDRAM_16Mx32_DDR2_CAS_N_pin, DIR = O
 PORT fpga_0_DDR2_SDRAM_16Mx32_DDR2_WE_N_pin = fpga_0_DDR2_SDRAM_16Mx32_DDR2_WE_N_pin, DIR = O
 PORT fpga_0_DDR2_SDRAM_16Mx32_DDR2_CS_N_pin = fpga_0_DDR2_SDRAM_16Mx32_DDR2_CS_N_pin, DIR = O
 PORT fpga_0_DDR2_SDRAM_16Mx32_DDR2_ODT_pin = fpga_0_DDR2_SDRAM_16Mx32_DDR2_ODT_pin, DIR = O
 PORT fpga_0_DDR2_SDRAM_16Mx32_DDR2_CKE_pin = fpga_0_DDR2_SDRAM_16Mx32_DDR2_CKE_pin, DIR = O
 PORT fpga_0_DDR2_SDRAM_16Mx32_DDR2_DM_pin = fpga_0_DDR2_SDRAM_16Mx32_DDR2_DM_pin, DIR = O, VEC = [3:0]
 PORT fpga_0_DDR2_SDRAM_16Mx32_DDR2_CK_pin = fpga_0_DDR2_SDRAM_16Mx32_DDR2_CK_pin, DIR = O, VEC = [1:0]
 PORT fpga_0_DDR2_SDRAM_16Mx32_DDR2_CK_N_pin = fpga_0_DDR2_SDRAM_16Mx32_DDR2_CK_N_pin, DIR = O, VEC = [1:0]
 PORT fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin = fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin, DIR = O
 PORT fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0_pin = fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0_pin, DIR = I
 PORT fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin = fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin, DIR = O, VEC = [7:0]
 PORT fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0_pin = fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0_pin, DIR = O
 PORT fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0_pin = fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0_pin, DIR = O
 PORT fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0_pin = fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0_pin, DIR = O
 PORT fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin = fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin, DIR = I, VEC = [7:0]
 PORT fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0_pin = fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0_pin, DIR = I
 PORT fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0_pin = fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0_pin, DIR = I
 PORT fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin = fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin, DIR = I
 PORT fpga_0_Hard_Ethernet_MAC_MDC_0_pin = fpga_0_Hard_Ethernet_MAC_MDC_0_pin, DIR = O
 PORT fpga_0_Hard_Ethernet_MAC_MDIO_0_pin = fpga_0_Hard_Ethernet_MAC_MDIO_0_pin, DIR = IO
 PORT fpga_0_Hard_Ethernet_MAC_PHY_MII_INT_pin = net_vcc, DIR = O
 PORT fpga_0_clk_1_sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
 PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1
 PORT custom_ip_tcp_0_slv_reg0_input_pin = custom_ip_tcp_0_slv_reg0_input, DIR = I, VEC = [0:31]
 PORT custom_ip_tcp_0_slv_reg1_input_pin = custom_ip_tcp_0_slv_reg1_input, DIR = I
 PORT custom_ip_tcp_0_slv_reg2_input_pin = custom_ip_tcp_0_slv_reg2_input, DIR = I
 PORT custom_ip_tcp_0_slv_reg3_input_pin = custom_ip_tcp_0_slv_reg3_input, DIR = I
 PORT custom_ip_tcp_0_slv_reg6_output_pin = custom_ip_tcp_0_slv_reg6_output, DIR = O
 PORT custom_ip_tcp_0_slv_reg4_output_pin = custom_ip_tcp_0_slv_reg4_output, DIR = O, VEC = [0:31]
 PORT custom_ip_tcp_0_slv_reg5_output_pin = custom_ip_tcp_0_slv_reg5_output, DIR = O
 PORT custom_ip_tcp_0_slv_reg7_output_pin = custom_ip_tcp_0_slv_reg7_output, DIR = O
 PORT IP_add_0_GPIO_IO_I_pin = IP_add_0_GPIO_IO_I, DIR = I, VEC = [0:15]
 PORT IP_add_1_GPIO_IO_I_pin = IP_add_1_GPIO_IO_I, DIR = I, VEC = [0:15]


BEGIN xps_intc
 PARAMETER INSTANCE = xps_intc_0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0x81800000
 PARAMETER C_HIGHADDR = 0x8180ffff
 BUS_INTERFACE SPLB = plb_v46_0
 PORT Intr = ppc440_0_DMA0TXIRQ & ppc440_0_DMA0RXIRQ & RS232_Interrupt & Hard_Ethernet_MAC_TemacIntc0_Irpt
 PORT Irq = ppc440_0_EICC440EXTIRQ
END

BEGIN bram_block
 PARAMETER INSTANCE = xps_bram_if_cntlr_1_bram
 PARAMETER C_FAMILY = virtex5
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
END

BEGIN xps_bram_if_cntlr
 PARAMETER INSTANCE = xps_bram_if_cntlr_1
 PARAMETER C_SPLB_NATIVE_DWIDTH = 32
 PARAMETER C_SPLB_SUPPORT_BURSTS = 1
 PARAMETER C_SPLB_P2P = 0
 PARAMETER C_FAMILY = virtex5
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_SPLB_SMALLEST_MASTER = 128
 PARAMETER C_BASEADDR = 0xfffc0000
 PARAMETER C_HIGHADDR = 0xffffffff
 BUS_INTERFACE SPLB = plb_v46_0
 BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
END

BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER HW_VER = 2.00.a
 BUS_INTERFACE RESETPPC0 = ppc_reset_bus
 PORT Slowest_sync_clk = clk_100_0000MHzPLL0_ADJUST
 PORT Ext_Reset_In = sys_rst_s
 PORT Dcm_locked = Dcm_all_locked
 PORT Bus_Struct_Reset = sys_bus_reset
 PORT Peripheral_Reset = sys_periph_reset
END

BEGIN ppc440_virtex5
 PARAMETER INSTANCE = ppc440_0
 PARAMETER C_IDCR_BASEADDR = 0b0000000000
 PARAMETER C_IDCR_HIGHADDR = 0b0011111111
 PARAMETER C_PPC440MC_ROW_CONFLICT_MASK = 0x000FFF80
 PARAMETER C_PPC440MC_BANK_CONFLICT_MASK = 0x00300000
 PARAMETER C_PPC440MC_CONTROL = 0xf850008f
 PARAMETER C_SPLB0_NUM_MPLB_ADDR_RNG = 0
 PARAMETER C_SPLB1_NUM_MPLB_ADDR_RNG = 0
 PARAMETER C_NUM_DMA = 1
 PARAMETER HW_VER = 1.01.a
 BUS_INTERFACE MPLB = plb_v46_0
 BUS_INTERFACE PPC440MC = ppc440_0_PPC440MC
 BUS_INTERFACE JTAGPPC = ppc440_0_jtagppc_bus
 BUS_INTERFACE RESETPPC = ppc_reset_bus
 BUS_INTERFACE LLDMA0 = Hard_Ethernet_MAC_LLINK0
 PORT CPMC440CLK = clk_400_0000MHzPLL0
 PORT CPMINTERCONNECTCLK = clk_200_0000MHzPLL0
 PORT CPMINTERCONNECTCLKNTO1 = net_vcc
 PORT EICC440EXTIRQ = ppc440_0_EICC440EXTIRQ
 PORT CPMMCCLK = clk_200_0000MHzPLL0_ADJUST
 PORT CPMPPCMPLBCLK = clk_100_0000MHzPLL0_ADJUST
 PORT CPMDMA0LLCLK = clk_100_0000MHzPLL0_ADJUST
 PORT DMA0TXIRQ = ppc440_0_DMA0TXIRQ
 PORT DMA0RXIRQ = ppc440_0_DMA0RXIRQ
 PORT CPMPPCS0PLBCLK = clk_100_0000MHzPLL0_ADJUST
END

BEGIN plb_v46
 PARAMETER INSTANCE = plb_v46_0
 PARAMETER C_DCR_INTFCE = 0
 PARAMETER C_FAMILY = virtex5
 PARAMETER HW_VER = 1.04.a
 PORT PLB_Clk = clk_100_0000MHzPLL0_ADJUST
 PORT SYS_Rst = sys_bus_reset
END

BEGIN jtagppc_cntlr
 PARAMETER INSTANCE = jtagppc_cntlr_inst
 PARAMETER HW_VER = 2.01.c
 BUS_INTERFACE JTAGPPC0 = ppc440_0_jtagppc_bus
END

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER C_CLKIN_FREQ = 100000000
 PARAMETER C_CLKOUT0_FREQ = 100000000
 PARAMETER C_CLKOUT0_PHASE = 0
 PARAMETER C_CLKOUT0_GROUP = PLL0_ADJUST
 PARAMETER C_CLKOUT0_BUF = TRUE
 PARAMETER C_CLKOUT1_FREQ = 125000000
 PARAMETER C_CLKOUT1_PHASE = 0
 PARAMETER C_CLKOUT1_GROUP = NONE
 PARAMETER C_CLKOUT1_BUF = TRUE
 PARAMETER C_CLKOUT2_FREQ = 200000000
 PARAMETER C_CLKOUT2_PHASE = 90
 PARAMETER C_CLKOUT2_GROUP = PLL0_ADJUST
 PARAMETER C_CLKOUT2_BUF = TRUE
 PARAMETER C_CLKOUT3_FREQ = 200000000
 PARAMETER C_CLKOUT3_PHASE = 0
 PARAMETER C_CLKOUT3_GROUP = PLL0
 PARAMETER C_CLKOUT3_BUF = TRUE
 PARAMETER C_CLKOUT4_FREQ = 200000000
 PARAMETER C_CLKOUT4_PHASE = 0
 PARAMETER C_CLKOUT4_GROUP = PLL0_ADJUST
 PARAMETER C_CLKOUT4_BUF = TRUE
 PARAMETER C_CLKOUT5_FREQ = 400000000
 PARAMETER C_CLKOUT5_PHASE = 0
 PARAMETER C_CLKOUT5_GROUP = PLL0
 PARAMETER C_CLKOUT5_BUF = TRUE
 PARAMETER HW_VER = 3.02.a
 PORT CLKIN = dcm_clk_s_bufg
 PORT CLKOUT0 = clk_100_0000MHzPLL0_ADJUST
 PORT CLKOUT1 = clk_125_0000MHz
 PORT CLKOUT2 = clk_200_0000MHz90PLL0_ADJUST
 PORT CLKOUT3 = clk_200_0000MHzPLL0
 PORT CLKOUT4 = clk_200_0000MHzPLL0_ADJUST
 PORT CLKOUT5 = clk_400_0000MHzPLL0
 PORT RST = net_gnd
 PORT LOCKED = Dcm_all_locked
END

BEGIN edk_bufg
 PARAMETER INSTANCE = clkin_bufg
 PARAMETER HW_VER = 1.00.a
 PORT in_clk = dcm_clk_s
 PORT out_clk = dcm_clk_s_bufg
END

BEGIN xps_uartlite
 PARAMETER INSTANCE = RS232
 PARAMETER C_FAMILY = virtex5
 PARAMETER C_BAUDRATE = 19200
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_ODD_PARITY = 0
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_BASEADDR = 0x84000000
 PARAMETER C_HIGHADDR = 0x8400ffff
 BUS_INTERFACE SPLB = plb_v46_0
 PORT RX = fpga_0_RS232_RX_pin
 PORT TX = fpga_0_RS232_TX_pin
 PORT Interrupt = RS232_Interrupt
END

BEGIN xps_ll_temac
 PARAMETER INSTANCE = Hard_Ethernet_MAC
 PARAMETER C_NUM_IDELAYCTRL = 2
 PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y5-IDELAYCTRL_X1Y5
 PARAMETER C_FAMILY = virtex5
 PARAMETER C_PHY_TYPE = 1
 PARAMETER C_TEMAC1_ENABLED = 0
 PARAMETER C_BUS2CORE_CLK_RATIO = 1
 PARAMETER C_TEMAC_TYPE = 0
 PARAMETER C_TEMAC0_PHYADDR = 0b00000000000000000000000000000001
 PARAMETER HW_VER = 2.03.a
 PARAMETER C_TEMAC0_TXFIFO = 32768
 PARAMETER C_TEMAC0_RXFIFO = 32768
 PARAMETER C_BASEADDR = 0x81c00000
 PARAMETER C_HIGHADDR = 0x81c7ffff
 BUS_INTERFACE SPLB = plb_v46_0
 BUS_INTERFACE LLINK0 = Hard_Ethernet_MAC_LLINK0
 PORT TemacIntc0_Irpt = Hard_Ethernet_MAC_TemacIntc0_Irpt
 PORT TemacPhy_RST_n = fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin
 PORT GTX_CLK_0 = clk_125_0000MHz
 PORT REFCLK = clk_200_0000MHzPLL0
 PORT LlinkTemac0_CLK = clk_100_0000MHzPLL0_ADJUST
 PORT MII_TX_CLK_0 = fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0_pin
 PORT GMII_TXD_0 = fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin
 PORT GMII_TX_EN_0 = fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0_pin
 PORT GMII_TX_ER_0 = fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0_pin
 PORT GMII_TX_CLK_0 = fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0_pin
 PORT GMII_RXD_0 = fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin
 PORT GMII_RX_DV_0 = fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0_pin
 PORT GMII_RX_ER_0 = fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0_pin
 PORT GMII_RX_CLK_0 = fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin
 PORT MDC_0 = fpga_0_Hard_Ethernet_MAC_MDC_0_pin
 PORT MDIO_0 = fpga_0_Hard_Ethernet_MAC_MDIO_0_pin
END

BEGIN ppc440mc_ddr2
 PARAMETER INSTANCE = DDR2_SDRAM_16Mx32
 PARAMETER C_DDR_BAWIDTH = 2
 PARAMETER C_NUM_CLK_PAIRS = 2
 PARAMETER C_DDR_DWIDTH = 32
 PARAMETER C_DDR_CAWIDTH = 9
 PARAMETER C_NUM_RANKS_MEM = 1
 PARAMETER C_CS_BITS = 0
 PARAMETER C_DDR_DM_WIDTH = 4
 PARAMETER C_DQ_BITS = 5
 PARAMETER C_DDR2_ODT_WIDTH = 1
 PARAMETER C_DDR2_ADDT_LAT = 1
 PARAMETER C_INCLUDE_ECC_SUPPORT = 0
 PARAMETER C_DQS_BITS = 2
 PARAMETER C_DDR_DQS_WIDTH = 4
 PARAMETER C_DDR_RAWIDTH = 13
 PARAMETER C_DDR_BURST_LENGTH = 4
 PARAMETER C_DDR_CAS_LAT = 3
 PARAMETER C_REG_DIMM = 0
 PARAMETER C_MIB_MC_CLOCK_RATIO = 1
 PARAMETER C_DDR_TREFI = 7800
 PARAMETER C_DDR_TRAS = 40000
 PARAMETER C_DDR_TRCD = 15000
 PARAMETER C_DDR_TRFC = 70000
 PARAMETER C_DDR_TRP = 15000
 PARAMETER C_DDR_TRTP = 7500
 PARAMETER C_DDR_TWR = 15000
 PARAMETER C_DDR_TWTR = 10000
 PARAMETER C_MC_MIBCLK_PERIOD_PS = 5000
 PARAMETER C_IDEL_HIGH_PERF = TRUE
 PARAMETER C_NUM_IDELAYCTRL = 2
 PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y3-IDELAYCTRL_X0Y4
 PARAMETER C_DQS_IO_COL = 0b00000000
 PARAMETER C_DQ_IO_MS = 0b10101010110101010101101010101010
 PARAMETER HW_VER = 2.00.b
 PARAMETER C_MEM_BASEADDR = 0x00000000
 PARAMETER C_MEM_HIGHADDR = 0x03ffffff
 BUS_INTERFACE PPC440MC = ppc440_0_PPC440MC
 PORT mc_mibclk = clk_200_0000MHzPLL0_ADJUST
 PORT mi_mcclk90 = clk_200_0000MHz90PLL0_ADJUST
 PORT mi_mcreset = sys_bus_reset
 PORT mi_mcclkdiv2 = clk_100_0000MHzPLL0_ADJUST
 PORT mi_mcclk_200 = clk_200_0000MHzPLL0
 PORT DDR2_DQ = fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQ_pin
 PORT DDR2_DQS = fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQS_pin
 PORT DDR2_DQS_N = fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQS_N_pin
 PORT DDR2_A = fpga_0_DDR2_SDRAM_16Mx32_DDR2_A_pin
 PORT DDR2_BA = fpga_0_DDR2_SDRAM_16Mx32_DDR2_BA_pin
 PORT DDR2_RAS_N = fpga_0_DDR2_SDRAM_16Mx32_DDR2_RAS_N_pin
 PORT DDR2_CAS_N = fpga_0_DDR2_SDRAM_16Mx32_DDR2_CAS_N_pin
 PORT DDR2_WE_N = fpga_0_DDR2_SDRAM_16Mx32_DDR2_WE_N_pin
 PORT DDR2_CS_N = fpga_0_DDR2_SDRAM_16Mx32_DDR2_CS_N_pin
 PORT DDR2_ODT = fpga_0_DDR2_SDRAM_16Mx32_DDR2_ODT_pin
 PORT DDR2_CKE = fpga_0_DDR2_SDRAM_16Mx32_DDR2_CKE_pin
 PORT DDR2_DM = fpga_0_DDR2_SDRAM_16Mx32_DDR2_DM_pin
 PORT DDR2_CK = fpga_0_DDR2_SDRAM_16Mx32_DDR2_CK_pin
 PORT DDR2_CK_N = fpga_0_DDR2_SDRAM_16Mx32_DDR2_CK_N_pin
END

BEGIN custom_ip_tcp_fifo
 PARAMETER INSTANCE = custom_ip_tcp_fifo_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0xcee00000
 PARAMETER C_HIGHADDR = 0xcee0ffff
 BUS_INTERFACE SPLB = plb_v46_0
 PORT slv_reg0_input = custom_ip_tcp_0_slv_reg0_input
 PORT slv_reg1_input = custom_ip_tcp_0_slv_reg1_input
 PORT slv_reg2_input = custom_ip_tcp_0_slv_reg2_input
 PORT slv_reg3_input = custom_ip_tcp_0_slv_reg3_input
 PORT slv_reg6_output = custom_ip_tcp_0_slv_reg6_output
 PORT slv_reg4_output = custom_ip_tcp_0_slv_reg4_output
 PORT slv_reg5_output = custom_ip_tcp_0_slv_reg5_output
 PORT slv_reg7_output = custom_ip_tcp_0_slv_reg7_output
END

BEGIN xps_gpio
 PARAMETER INSTANCE = IP_add_0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_GPIO_WIDTH = 16
 PARAMETER C_ALL_INPUTS = 1
 PARAMETER C_BASEADDR = 0x81420000
 PARAMETER C_HIGHADDR = 0x8142ffff
 BUS_INTERFACE SPLB = plb_v46_0
 PORT GPIO_IO_I = IP_add_0_GPIO_IO_I
END

BEGIN xps_gpio
 PARAMETER INSTANCE = IP_add_1
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_GPIO_WIDTH = 16
 PARAMETER C_ALL_INPUTS = 1
 PARAMETER C_BASEADDR = 0x81400000
 PARAMETER C_HIGHADDR = 0x8140ffff
 BUS_INTERFACE SPLB = plb_v46_0
 PORT GPIO_IO_I = IP_add_1_GPIO_IO_I
END

BEGIN xps_timer
 PARAMETER INSTANCE = xps_timer_0
 PARAMETER HW_VER = 1.01.b
 PARAMETER C_BASEADDR = 0x83c00000
 PARAMETER C_HIGHADDR = 0x83c0ffff
 BUS_INTERFACE SPLB = plb_v46_0
END






---- MSS ----

 PARAMETER VERSION = 2.2.0


BEGIN OS
 PARAMETER OS_NAME = standalone
 PARAMETER OS_VER = 2.00.a
 PARAMETER PROC_INSTANCE = ppc440_0
 PARAMETER stdin = RS232
 PARAMETER stdout = RS232
END


BEGIN PROCESSOR
 PARAMETER DRIVER_NAME = cpu_ppc440
 PARAMETER DRIVER_VER = 1.01.a
 PARAMETER HW_INSTANCE = ppc440_0
 PARAMETER COMPILER = powerpc-eabi-gcc
 PARAMETER ARCHIVER = powerpc-eabi-ar
END


BEGIN DRIVER
 PARAMETER DRIVER_NAME = memcon
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = DDR2_SDRAM_16Mx32
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = bram
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = xps_bram_if_cntlr_1
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = xps_bram_if_cntlr_1_bram
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = uartlite
 PARAMETER DRIVER_VER = 1.14.a
 PARAMETER HW_INSTANCE = RS232
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = lltemac
 PARAMETER DRIVER_VER = 1.00.b
 PARAMETER HW_INSTANCE = Hard_Ethernet_MAC
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = clock_generator_0
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = jtagppc_cntlr_inst
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = proc_sys_reset_0
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = intc
 PARAMETER DRIVER_VER = 1.11.a
 PARAMETER HW_INSTANCE = xps_intc_0
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = plb_v46_0
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = custom_ip_tcp_fifo
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = custom_ip_tcp_fifo_0
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = gpio
 PARAMETER DRIVER_VER = 2.13.a
 PARAMETER HW_INSTANCE = IP_add_0
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = gpio
 PARAMETER DRIVER_VER = 2.13.a
 PARAMETER HW_INSTANCE = IP_add_1
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = tmrctr
 PARAMETER DRIVER_VER = 1.11.a
 PARAMETER HW_INSTANCE = xps_timer_0
END


BEGIN LIBRARY
 PARAMETER LIBRARY_NAME = xilmfs
 PARAMETER LIBRARY_VER = 1.00.a
 PARAMETER base_address = 0x03000000
 PARAMETER PROC_INSTANCE = ppc440_0
 PARAMETER need_utils = true
 PARAMETER numbytes = 266000
 PARAMETER init_type = MFSINIT_IMAGE
END

BEGIN LIBRARY
 PARAMETER LIBRARY_NAME = lwip130
 PARAMETER LIBRARY_VER = 1.00.b
 PARAMETER PROC_INSTANCE = ppc440_0
 PARAMETER mem_size = 1310720
 PARAMETER pbuf_pool_size = 512
 PARAMETER pbuf_pool_bufsize = 8192
 PARAMETER ip_frag_max_mtu = 8192
 PARAMETER tcp_wnd = 64240
 PARAMETER tcp_snd_buf = 18192
 PARAMETER tcp_mss = 8192
END


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by:DBTechnique
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Does it help you, or do you need more information?
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HappyCactus earned 500 total points
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I think that it's impossible to help you without having the hardware to check.
Follow my previous - although general - suggestions. And check the IP core documentation about DMA support of the eth controller and the CPU.

Hope that helps
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by:DBTechnique
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ok thank you
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Author Closing Comment

by:DBTechnique
Comment Utility
maybe my question was not enough sharp
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