Assume we have a simple system with a CPU (including an on-chip TLB), a single cache and main memory. The latencies for the TLB, cache and main memory are 1, 10 and 100 ns, respectively. These times include time for accessing any element 'on the way' to the given element.
o What is the 'worst' case time for accessing program data? Explain your answer.
o What is the 'best' case time for access program data? Explain your answer.
o Which of these cases (best or worst) would you expect for the first data access in a given program? Why?
I just wanted to make sure my thinking process was correct. I think the 'worst' case is 111 ns, while the 'best' case is 1 ns.