Makefile use of ifdef

Is it possible for a makefile to be aware of what is defined in the source code?  For example, in a header file I have:
#define T5

I'd like the makefile to recognize the definition and build differently based on that:
ifdef T5
CH_Manager: $(OBJ)
      $(CC) $(CCOPT) $(CFLAGS) -o $(OUTDIR)CH_Manager_T5 $^
endif

This doesn't work.  
I'd like to change the name of the resulting executable based on what's defined. Is it possible?  If not is there another way to do it?

Thanks.
JohnSantaFeAsked:
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jkrCommented:
You can use 'ifdef' in your makefile to set a definition for the source code, that to me seems the better way round:

ifdef T5
CH_Manager: $(OBJ)
      $(CC) $(CCOPT) $(CFLAGS) -DT5 -o $(OUTDIR)CH_Manager_T5 $^
endif
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JohnSantaFeAuthor Commented:
Yea, I understand that.  The disadvantage is you don't get the highlighting in the IDE (Eclipse) that shows you what is being defined and what is not.  I find that very useful.
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Infinity08Commented:
The traditional (unix) approach to this, is to have a configure script that is run before building the source code, and serves to customize the build for the specific platform and/or user preferences.

See eg. autoconf (http://www.gnu.org/software/autoconf/) for a tool that facilitates the generation of such configure scripts.

The configure script would generate a config.h file, which your IDE can read, and provide the highlighting you desire.
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sarabandeCommented:
you could make a new target in the makefile

T5:  $(EXE)
      sometool  $(EXE) -T5

Open in new window


it is assumed that $(EXE) is the target which makes the executable. sometool would check whether the executable has the option defined - for example by reading the configuration or simply by starting the executable with a special option - and if so would copy or rename the executable.

Sara
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JohnSantaFeAuthor Commented:
I appreciate the ideas.  It looks like the 'right' way to do this is with autoconf, I was hoping for something a little simpler.
Thanks.
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