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Compile and link when dependent header file changed in other directory...

Posted on 2012-08-26
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Last Modified: 2013-12-20
Dear experts,
I have 3 questions about compiling and linking my project in fewer steps...

@ My project looks like: ( I use Watcom C to compile//link the project )

Directory 'MyProject' ( within it there are 3 sub directories for different modules )
- directory 'A' ( a.h and a.c included )
- directory 'B' ( b.h and b.c included )
- directory 'C' ( c.h and c.c included )
- my.c and my.h
- my.lnk file
- makefile

And within each sub directory there is one corresponding makefile...

[Q1] Assume I update a.h in directory A and a.h is referenced by b.c in directory B, then my original steps will be:

1. compile in directory A ( obj and lib generated...)
2. compile in directory B ( obj and lib generated...)
3. back to directory MyProject then compile and link

Is there any "faster" way ?

[Q2] If I want to ignore all existing obj/lib and rebuild all, how to do it ?
* I know this takes time but sometimes "kill and rebuild" will be better...

[Q3] If my.h is updated and it is referenced by a.c,b.c, and c.c...
Is there any faster way to compile and link ?

Notes:
* The makefile in sub directory(A,B,or C) looks like below:
INCLUDE1 = -ic:\watcom\h
OBJECTS1 = a.obj
CFLAGS   = -zq -mf -oxsbl $(INCLUDE1)
DEST     = a.exe
COMPILER = wpp386

.erase # special cmd, tell wmake to "erase" target if make is not successful

.cpp.obj: .AUTODEPEND
               $(COMPILER) $(CFLAGS) $<

$(DEST) : $(OBJECTS1) makefile

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*  The makefile in main directory looks like below:
INCLUDE1 = -i=c:\myproj\my -i=c:\watcom\h 
OBJECTS1 = my.obj
CFLAGS   = -zq -fp6 -mf -6r -s -oxsbl $(INCLUDE1)
DEST     = my.exe
COMPILER = wpp386
LINKER   = wlink
LNK_FILE = my.lnk

.erase # special cmd, tell wmake to "erase" target if make is not successful

.cpp.obj: .AUTODEPEND
      $(COMPILER) $(CFLAGS) $<


$(DEST) : $(OBJECTS1) makefile my.lnk
      $(LINKER) @$(LNK_FILE) 

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Note: My project works well and fine and I just want to find faster steps when compiling and linking...

Thanks !
liaoo
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Question by:liaoo
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3 Comments
 
LVL 35

Assisted Solution

by:Duncan Roe
Duncan Roe earned 1500 total points
ID: 38358082
1. You don't say which vendor's make you are using, but certainly with GNU make and gcc you could generate dependency files automatically. You could still then compile them with watcom.
2. You need your makefiles to include a clean target. Then make clean; make (Bourne shell) or make clean & make (Windows CMD.EXE) will rebuild.
3. Your top-level makefile needs to invoke make in each sub directory. It needs to pass its command-line arguments (e.g. clean).

samples in following posts
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LVL 35

Assisted Solution

by:Duncan Roe
Duncan Roe earned 1500 total points
ID: 38358130
This short makefile builds the Q editor
.PHONY: clean
SRCS = $(wildcard *.c)
OBJ = $(SRCS:.c=.o)
CPPFLAGS = -DANSI5 $(shell getconf LFS_CFLAGS)
CFLAGS = -g3 -ggdb \
  -Wall -Wshadow -Wpointer-arith -Wcast-qual -Wcast-align -Wstrict-prototypes \
  -Wmissing-prototypes
q : $(OBJ)
        $(CC) $^ -o $@
clean :
        rm -f *.o *.d q

# Auto dependency stuff (from info make)
%.d: %.c
        gcc -MM -MT $(@:.d=.o) -MT $@ $(CPPFLAGS) $< > $@
ifneq ($(MAKECMDGOALS),clean)
-include $(SRCS:.c=.d)
endif

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1. Auto dependencies

This is handled from line 14 onwards. For each .o target, use gcc to create a file which can be used by make as a dependency. As an example, it made this q.d
q.o q.d: q.c alledit.h ckalloc.h edmast.h macros.h termio5.hl c1in.h

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Lines 16 & 18 are a recent embellishment to avoid making dependencies for the clean target.

2. Creating a [i]clean[/i] target

Lines 10 & 11 implement the clean target. All it does is delete all generated intermediary files and the built program. This is a typical action, although some might prefer to have clean not  delete the built program and have some other target (e.g. reallyclean) which deletes it as well as the intermediaries.
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LVL 35

Accepted Solution

by:
Duncan Roe earned 1500 total points
ID: 38358148

3. Sample recursive makefiles

This is a Makefile in a subdirectory
.PHONY: all clean
all:
        @echo all
clean:
        @echo clean

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Its only purpose is to demonstrate that it was called with the right target: either all (which is the default target by virtue of coming first and therefore doesn't need to be named explicitly); or clean
13:13:53$ make
all
13:16:35$ make all
all
13:16:39$ make clean
clean

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This is the top-level Makefile
.PHONY: all clean
clean : all
all:
        @cd s1 && $(MAKE) $(MAKECMDGOALS); cd ..; \
        cd s2 && $(MAKE) $(MAKECMDGOALS); cd ..; \
        cd s2 && $(MAKE) $(MAKECMDGOALS); cd ..

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Its only function is to invoke make in 3 subdirectories s1, s2s3 (which all have identical Makefiles). Testing it as before
13:24:28$ make
make[1]: Entering directory `/home/dunc/tests/ee92/s1'
all
make[1]: Leaving directory `/home/dunc/tests/ee92/s1'
make[1]: Entering directory `/home/dunc/tests/ee92/s2'
all
make[1]: Leaving directory `/home/dunc/tests/ee92/s2'
make[1]: Entering directory `/home/dunc/tests/ee92/s2'
all
make[1]: Leaving directory `/home/dunc/tests/ee92/s2'
13:24:30$ make all
make[1]: Entering directory `/home/dunc/tests/ee92/s1'
all
make[1]: Leaving directory `/home/dunc/tests/ee92/s1'
make[1]: Entering directory `/home/dunc/tests/ee92/s2'
all
make[1]: Leaving directory `/home/dunc/tests/ee92/s2'
make[1]: Entering directory `/home/dunc/tests/ee92/s2'
all
make[1]: Leaving directory `/home/dunc/tests/ee92/s2'
13:24:34$ make clean
make[1]: Entering directory `/home/dunc/tests/ee92/s1'
clean
make[1]: Leaving directory `/home/dunc/tests/ee92/s1'
make[1]: Entering directory `/home/dunc/tests/ee92/s2'
clean
make[1]: Leaving directory `/home/dunc/tests/ee92/s2'
make[1]: Entering directory `/home/dunc/tests/ee92/s2'
clean
make[1]: Leaving directory `/home/dunc/tests/ee92/s2'

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The Makefiles in the subdirectories are invoked with the correct target.Please post for further explanation of any of the above
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