query on RISC/CISC binary on single hardware

Posted on 2012-09-14
Last Modified: 2012-09-24
I know that compilers on Intel x86 architecture generate only CISC binaries, because Intel x86 is providing CISC assembly variable instructions.

But i see that, hp NSK s-series supports both CISC and RISC binaries, their NMC compiler generates RISC instructions of c code, their C compiler generates CISC instructions of C code.

But i am not clear how a s-series hardware provides both CISC as well as RISC instruction set to execute on its hardware? am confused.

Question by:mohet01
    LVL 82

    Expert Comment

    by:Dave Baldwin
    It's really not as simple as CISC and RISC.  At least not anymore.  In the 1980's, assembly language corresponded directly to the registers and functions available in the CPUs.  Modern CPU are almost interpreters of the 'machine language' instructions.  In order to support features such as branch prediction and fast register switching, there are many more registers and functions in a CPU than the programmer can address directly.

    And they can load 'microcode' that implements new features in the CPU, or fixes errors in the CPU, or maybe even changes the whole assembly language if they want.  So it is no problem featuring programming that acts as CISC one time and RISC another time.  And if you have multiple CPU cores, I guess you could do both at the same time.

    Author Comment

    So, you mean to say that intel x86 also has capability to support both CISC and RISC instruction set?
    LVL 82

    Accepted Solution

    If Intel wanted to do that, I'm sure they could.  I doubt that they will though, that's not where they make their money.  Although...

    From :

    Even some CISC processors (based on architectures that were created before RISC became dominant), such as newer x86 processors, translate instructions internally into a RISC-like instruction set.

    Author Comment

    "newer x86 processors, translate instructions internally into a RISC-like instruction set."

    i think microcode in control stroe in new x86 processors would be doing all this magic

    Author Closing Comment


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