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AIX NUMA

Posted on 2014-01-22
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so NUMA..
we have a p780 that host our lpar for one of our oracle prod DB..

this command is showing

lssrad -va                  
REF1   SRAD        MEM      CPU
0
          0   141814.44      0-47 52-55 60-63 68-71 76-79 84-87 92-95
          1   54702.00      48-51 56-59 64-67 72-75 80-83 88-91 96-99

so that menas we have only 2 NUMA domains?

do we need to pursuit any tuning? how can we decide? and what to check?
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Question by:it-rex
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by:woolmilkporc
ID: 39801420
You have two SRADS (Scheduler Resource Affinity Domains) because you have two hardware sockets (MCM modules) in your machine.

You can only increase the number of SRADs by buying/installing more sockets/MCMs.
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by:it-rex
ID: 39801435
do we need to pursuit any tuning? how can we decide? and what to check?
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by:woolmilkporc
ID: 39801514
The fewer SRADs in a virtual machine the better.
Lpars should be spread in the minimum number of Chips / Nodes to
reduce the number of Remote & Distant Memory.

Optimizing LPAR placement is quite a complicated task.

Here is a developerworks blog on that topic:
https://www.ibm.com/developerworks/community/blogs/aixpert/entry/local_near_far_power7_affinity_nine_conclusions17?lang=en

During LPAR creation on the HMC you can associate an LPAR with an affinity group.
Put critical LPARs in an affinity group of their own, a single LPAR per group.
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by:it-rex
ID: 39801571
so the differnce in memory assigened to each domain

     0   141814.44     0-47 52-55 60-63 68-71 76-79 84-87 92-95
          1   54702.00      48-51 56-59 64-67 72-75 80-83 88-91 96-99

is it something to worry about?
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woolmilkporc earned 2000 total points
ID: 39801621
I don't know how much memory you have in your machine per socket/MCM
.
If the LPAR demands more memory than can be provided by one physical socket then there is no way around splitting memory across SRADs.

Memory in one SRAD needed by a thread running on a core in the other SRAD is considered "near" or "far"  memory as opposed to "local" memory.
In your case both SRADs are in the same building block (because they're both in REF1 (Node) 0) so we're talking about "near" memory - access to near memory has to go through the "Power Chip to Power Chip Intra-node communication path" which shouldn't cost much time.

The fundamental proposition is still: The fewer SRADs the better. See my hints on LPAR placement optimization.
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by:it-rex
ID: 39801639
thanks
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