Linux Makefile

Suppose the following files are in the current directory, (hellomake.c, hellofunc.c and hellomake.h)

Inside the makefile :
CC=gcc
CFLAGS=-I.
DEPS = hellomake.h
%.o: %.c $(DEPS)
$(CC) -c -o $@ $< $(CFLAGS)

hellomake: hellomake.o hellofunc.o
gcc -o hellomake hellomake.o hellofunc.o -I.

What will be replaced in the line "$(CC) -c -o $@ $< $(CFLAGS)" ?

Thanks
AXISHKAsked:
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gheistCommented:
Is it a exam question?
Zephyr ICTCloud ArchitectCommented:
What do you mean with "replaced"? As in files, or what the variables mean?

Like $(CC)= gcc for example?
Zephyr ICTCloud ArchitectCommented:

Is it a exam question?

Would think so wouldn't you :)
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gheistCommented:
Just that what is written reflects what gnu make already knows - make .o from .c file
AXISHKAuthor Commented:
No, this is just seen in an article about makefile..

$(CC) -c -o $@ $< $(CFLAGS)

will be translated as

gcc -c -o hellomake.o -I
gcc -c -o hellofunc.o -I

ie, gcc will find xxx.c and complie it to the corresponding object file, xxx.o ... correct ?
gheistCommented:
gmake knows that line without makefile
if you say
make x.o
it will run gcc x.c -o x.o
see http://c.learncodethehardway.org/book
AXISHKAuthor Commented:
Tks, but I want to clarify what does the line do in makefile,

$(CC) -c -o $@ $< $(CFLAGS)

Tks again.
gheistCommented:
Read first 3 pages of book I sent to you in a link... It answers your question.
AXISHKAuthor Commented:
Thanks, but i still can't sure whether my understanding is correct or not..

Will the command line
$(CC) -c -o $@ $< $(CFLAGS)

 be translated as

 gcc -c -o hellomake.o -I
 gcc -c -o hellofunc.o -I

and gcc will automatically look for the source code hellomake.c and hellofunc.c respectively ? Tks
gheistCommented:
make looks for the file and makes accurate parameters for gcc

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