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Designing routers or switches which support 100 Gbit/s interfaces is difficult. The need to process a 100 Gbit/s stream of packets at line rate without reordering within IP/MPLS microflows is one reason for this.
As of 2011, most components in the 100 Gbit/s packet processing path (PHY chips, NPUs, memories) were not readily available off-the-shelf or require extensive qualification and co-design. Another problem is related to the low-output production of 100 Gbit/s optical components, which were also not easily available – especially in pluggable, long-reach or tunable laser flavors.
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